Xilinx Design Summary

top Project Status (06/21/2014 - 00:02:15)
Project File: | top.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Programming File Generated

Target Device:

xc6slx9-3tqg144

- Errors:

No Errors

Product Version:

ISE 14.7

- Warnings:

119 Warnings (26 new)

Design Goal:

Balanced

- Routing Results:

All Signals Completely Routed

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

All Constraints Met

Environment:

System Settings

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 296 | 11,440 | 2% |
Number used as Flip Flops | 296 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 318 | 5,720 | 5% |
Number used as logic | 278 | 5,720 | 4% |
Number using O6 output only | 78 |  |  |
Number using O5 output only | 147 |  |  |
Number using O5 and O6 | 53 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 1 | 1,440 | 1% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 1 |  |  |
Number using O6 output only | 1 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used exclusively as route-thrus | 39 |  |  |
Number with same-slice register load | 32 |  |  |
Number with same-slice carry load | 7 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 106 | 1,430 | 7% |
Number of MUXCYs used | 200 | 2,860 | 6% |
Number of LUT Flip Flop pairs used | 340 |  |  |
Number with an unused Flip Flop | 81 | 340 | 23% |
Number with an unused LUT | 22 | 340 | 6% |
Number of fully used LUT-FF pairs | 237 | 340 | 69% |
Number of unique control sets | 17 |  |  |
Number of slice register sites lost to control set restrictions | 47 | 11,440 | 1% |
Number of bonded IOBs | 21 | 102 | 20% |
Number of LOCed IOBs | 21 | 21 | 100% |
Number of RAMB16BWERs | 0 | 32 | 0% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 3 | 16 | 18% |
Number used as BUFGs | 3 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 2.54 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周六 六月 21 00:01:09 2014 | 0 | 114 Warnings (24 new) | 4 Infos (0 new)
Translation Report | Current | 周六 六月 21 00:01:16 2014 | 0 | 0 | 0
Map Report | Current | 周六 六月 21 00:01:34 2014 | 0 | 1 Warning (0 new) | 8 Infos (1 new)
Place and Route Report | Current | 周六 六月 21 00:01:45 2014 | 0 | 4 Warnings (2 new) | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | 周六 六月 21 00:01:52 2014 | 0 | 0 | 4 Infos (0 new)
Bitgen Report | Current | 周六 六月 21 00:02:03 2014 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | 周六 六月 21 00:02:04 2014
WebTalk Log File | Current | 周六 六月 21 00:02:15 2014

Date Generated: 06/21/2014 -