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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
samp_ram YourInstanceName (
	.clka(clka), // input clka
	.wea(wea), // input [0 : 0] wea
	.addra(addra), // input [9 : 0] addra
	.dina(dina), // input [15 : 0] dina
	.douta(douta), // ouput [15 : 0] douta
	.clkb(clkb), // input clkb
	.web(web), // input [0 : 0] web
	.addrb(addrb), // input [9 : 0] addrb
	.dinb(dinb), // input [15 : 0] dinb
	.doutb(doutb)); // ouput [15 : 0] doutb

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file samp_ram.v when simulating
// the core, samp_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

