<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/brst_cntr.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/cslt_cntr.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/ki_cntr.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/rcd_cntr.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/ref_cntr.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sdrm.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sdrm.v</arg>&quot; Line <arg fmt="%d" index="2">21</arg>. <arg fmt="%s" index="3">Include file found: &apos;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&apos; in file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sdrm.v&quot; line 21
</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sdrm_t.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sdrmc_state.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sys_int.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1065" >&quot;<arg fmt="%s" index="1">E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sys_int.v</arg>&quot; Line <arg fmt="%d" index="2">20</arg>. <arg fmt="%s" index="3">Include file found: &apos;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/define.v&apos; in file &quot;E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/sdram_ver_134/sys_int.v&quot; line 20
</arg>
</msg>

</messages>

