Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\vga.v" into library work
Parsing module <vga_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\led.v" into library work
Parsing module <led_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\key.v" into library work
Parsing module <key_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ir.v" into library work
Parsing module <ir_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ipcore_dir\clk_pll.v" into library work
Parsing module <clk_pll>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\dt.v" into library work
Parsing module <dt_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\beep.v" into library work
Parsing module <beep_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ad.v" into library work
Parsing module <ad_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" into library work
Parsing module <top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <top>.

Elaborating module <clk_pll>.

Elaborating module <BUFG>.

Elaborating module <PLL_BASE(BANDWIDTH="OPTIMIZED",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="SYSTEM_SYNCHRONOUS",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=10,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=12,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT1_DIVIDE=30,CLKOUT1_PHASE=0.0,CLKOUT1_DUTY_CYCLE=0.5,CLKOUT2_DIVIDE=94,CLKOUT2_PHASE=0.0,CLKOUT2_DUTY_CYCLE=0.5,CLKIN_PERIOD=20.833,REF_JITTER=0.01)>.
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ipcore_dir\clk_pll.v" Line 126: Assignment to clkout3_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ipcore_dir\clk_pll.v" Line 127: Assignment to clkout4_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ipcore_dir\clk_pll.v" Line 128: Assignment to clkout5_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" Line 57: Assignment to clk5m12 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" Line 65: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" Line 73: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" Line 82: Result of 4-bit expression is truncated to fit in 3-bit target.

Elaborating module <led_module>.

Elaborating module <beep_module>.

Elaborating module <key_module>.

Elaborating module <dt_module>.

Elaborating module <ir_module>.
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ir.v" Line 130: Assignment to T_Value ignored, since the identifier is never used

Elaborating module <ad_module>.

Elaborating module <vga_module>.
WARNING:HDLCompiler:1127 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\vga.v" Line 109: Assignment to PIX ignored, since the identifier is never used

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v".
INFO:Xst:3210 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" line 52: Output port <CLK_OUT3> of the instance <pll_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\top.v" line 52: Output port <LOCKED> of the instance <pll_inst> is unconnected or connected to loadless signal.
    Found 7-bit register for signal <cnt_5m12>.
    Found 3-bit register for signal <cnt_5k>.
    Found 32-bit register for signal <cnt>.
    Found 1-bit register for signal <num_dt<3><3>>.
    Found 1-bit register for signal <num_dt<3><2>>.
    Found 1-bit register for signal <num_dt<3><1>>.
    Found 1-bit register for signal <num_dt<3><0>>.
    Found 1-bit register for signal <num_dt<2><3>>.
    Found 1-bit register for signal <num_dt<2><2>>.
    Found 1-bit register for signal <num_dt<2><1>>.
    Found 1-bit register for signal <num_dt<2><0>>.
    Found 1-bit register for signal <num_dt<1><3>>.
    Found 1-bit register for signal <num_dt<1><2>>.
    Found 1-bit register for signal <num_dt<1><1>>.
    Found 1-bit register for signal <num_dt<1><0>>.
    Found 1-bit register for signal <num_dt<0><3>>.
    Found 1-bit register for signal <num_dt<0><2>>.
    Found 1-bit register for signal <num_dt<0><1>>.
    Found 1-bit register for signal <num_dt<0><0>>.
    Found 4-bit register for signal <cnt_16m>.
    Found 4-bit adder for signal <cnt_16m[3]_GND_1_o_add_1_OUT> created at line 65.
    Found 7-bit adder for signal <cnt_5m12[6]_GND_1_o_add_4_OUT> created at line 73.
    Found 3-bit adder for signal <cnt_5k[2]_GND_1_o_add_7_OUT> created at line 82.
    Found 32-bit adder for signal <cnt[31]_GND_1_o_add_15_OUT> created at line 185.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  62 D-type flip-flop(s).
Unit <top> synthesized.

Synthesizing Unit <clk_pll>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ipcore_dir\clk_pll.v".
    Summary:
	no macro.
Unit <clk_pll> synthesized.

Synthesizing Unit <led_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\led.v".
        SEC_TIME = 32'b00000010110111000110110000000000
    Found 1-bit register for signal <clk_hz>.
    Found 4-bit register for signal <led_reg>.
    Found 32-bit register for signal <cnt1>.
    Found 32-bit adder for signal <cnt1[31]_GND_5_o_add_2_OUT> created at line 35.
    Found 16x4-bit Read Only RAM for signal <PWR_5_o_PWR_5_o_mux_16_OUT>
    Found 1-bit tristate buffer for signal <led<3>> created at line 56
    Found 1-bit tristate buffer for signal <led<2>> created at line 56
    Found 1-bit tristate buffer for signal <led<1>> created at line 56
    Found 1-bit tristate buffer for signal <led<0>> created at line 56
    HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <led_reg> would allow inference of a finite state machine and as consequence better performance and smaller area.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  37 D-type flip-flop(s).
	inferred   4 Tristate(s).
Unit <led_module> synthesized.

Synthesizing Unit <beep_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\beep.v".
        DIV_KHZ = 32'b00000000000000001011101110000000
    Found 1-bit register for signal <clk_1k>.
    Found 32-bit register for signal <cnt_khz>.
    Found 32-bit adder for signal <cnt_khz[31]_GND_10_o_add_2_OUT> created at line 26.
    Found 1-bit tristate buffer for signal <beep> created at line 28
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <beep_module> synthesized.

Synthesizing Unit <key_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\key.v".
        DIV_FACTOR = 32'b00000000000000001011101110000000
    Found 1-bit register for signal <clk_khz>.
    Found 32-bit register for signal <key_reg0>.
    Found 32-bit register for signal <key_reg1>.
    Found 32-bit register for signal <key_reg2>.
    Found 32-bit register for signal <key_reg3>.
    Found 32-bit register for signal <cnt>.
    Found 32-bit adder for signal <cnt[31]_GND_12_o_add_2_OUT> created at line 29.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 161 D-type flip-flop(s).
Unit <key_module> synthesized.

Synthesizing Unit <dt_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\dt.v".
        NUM_0 = 7'b0111111
        NUM_1 = 7'b0000110
        NUM_2 = 7'b1011011
        NUM_3 = 7'b1001111
        NUM_4 = 7'b1100110
        NUM_5 = 7'b1101101
        NUM_6 = 7'b1111101
        NUM_7 = 7'b0000111
        NUM_8 = 7'b1111111
        NUM_9 = 7'b1101111
        NUM_A = 7'b1110111
        NUM_B = 7'b1111100
        NUM_C = 7'b1011000
        NUM_D = 7'b1011110
        NUM_E = 7'b1111001
        NUM_F = 7'b1110001
        NUM_BLK = 7'b0000000
        EN_1 = 4'b1110
        EN_2 = 4'b1101
        EN_3 = 4'b1011
        EN_4 = 4'b0111
        EN_A = 4'b0000
    Found 7-bit register for signal <ds_reg>.
    Found 4-bit register for signal <ds_en>.
    Found 32-bit register for signal <cnt>.
    Found 32-bit adder for signal <cnt[31]_GND_13_o_add_1_OUT> created at line 59.
    Found 4x4-bit Read Only RAM for signal <ds_en[3]_num4[3]_mux_23_OUT>
    Found 7-bit 4-to-1 multiplexer for signal <ds_reg[6]_num4[3]_mux_22_OUT> created at line 124.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <dt_module> synthesized.

Synthesizing Unit <ir_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ir.v".
        ST_START_L = 3'b000
        ST_CODE_P = 3'b001
        ST_VALUE_P = 3'b010
        ST_START_H = 3'b011
        ST_CODE_N = 3'b100
        ST_VALUE_N = 3'b101
        START_H = 16'b0001000000000000
        START_L = 16'b0010000000000000
        CODE_0 = 16'b0000010000000000
        CODE_1 = 16'b0000100000000000
    Found 16-bit register for signal <cnt_l>.
    Found 16-bit register for signal <cnt_h>.
    Found 1-bit register for signal <Flag_LVL>.
    Found 1-bit register for signal <Flag_HVL>.
    Found 16-bit register for signal <cnt_val>.
    Found 16-bit register for signal <IR_code>.
    Found 6-bit register for signal <cnt_num>.
    Found 3-bit register for signal <state>.
    Found 32-bit register for signal <IR_Value>.
    Found 8-bit register for signal <Code>.
    Found 3-bit register for signal <IR_reg>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 17                                             |
    | Inputs             | 8                                              |
    | Outputs            | 3                                              |
    | Clock              | clk_1m (rising_edge)                           |
    | Power Up State     | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <cnt_l[15]_GND_14_o_add_10_OUT> created at line 69.
    Found 16-bit adder for signal <cnt_h[15]_GND_14_o_add_15_OUT> created at line 88.
    Found 16-bit adder for signal <cnt_val[15]_GND_14_o_add_25_OUT> created at line 120.
    Found 6-bit adder for signal <cnt_num[5]_GND_14_o_add_47_OUT> created at line 162.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 115 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <ir_module> synthesized.

Synthesizing Unit <ad_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\ad.v".
    Found 1-bit register for signal <adc_clk_valid>.
    Found 1-bit register for signal <adc_cs_n>.
    Found 8-bit register for signal <adc_data_buf>.
    Found 8-bit register for signal <adc_data>.
    Found 4-bit register for signal <cnt>.
    Found 4-bit adder for signal <cnt[3]_GND_15_o_add_3_OUT> created at line 34.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  22 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <ad_module> synthesized.

Synthesizing Unit <vga_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\logic\0-example_test_board_x\vga.v".
        RED = 32'b00000000000000000000000000011111
        GREEN = 32'b00000000000000000000011111100000
        BLUE = 32'b00000000000000001111000100000000
        WHITE = 32'b00000000000000001111111111111111
        BLACK = 32'b00000000000000000000000000000000
        H_PIXELS = 32'b00000000000000000000001100100100
        H_FRONTPORCH = 32'b00000000000000000000000000101000
        H_SYNCTIME = 32'b00000000000000000000000010000000
        H_BACKPORCH = 32'b00000000000000000000000001011000
        H_SYNCSTART = 32'b00000000000000000000001110000100
        H_SYNCEND = 32'b00000000000000000000010000000100
        H_PERIOD = 32'b00000000000000000000010000100000
        V_LINES = 32'b00000000000000000000001001011100
        V_FRONTPORCH = 32'b00000000000000000000000000000001
        V_SYNCTIME = 32'b00000000000000000000000000000100
        V_BACKPORCH = 32'b00000000000000000000000000010111
        V_SYNCSTART = 32'b00000000000000000000001001011011
        V_SYNCEND = 32'b00000000000000000000001001011111
        V_PERIOD = 32'b00000000000000000000001001110100
    Found 16-bit register for signal <PColor>.
    Found 1-bit register for signal <hsyncint>.
    Found 12-bit register for signal <vcnt>.
    Found 1-bit register for signal <vsync>.
    Found 1-bit register for signal <enable>.
    Found 16-bit register for signal <pixel>.
    Found 12-bit register for signal <hcnt>.
    Found 12-bit adder for signal <hcnt[11]_GND_16_o_add_2_OUT> created at line 70.
    Found 12-bit adder for signal <vcnt[11]_GND_16_o_add_10_OUT> created at line 87.
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_2_o> created at line 69
    Found 12-bit comparator lessequal for signal <n0004> created at line 76
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_8_o> created at line 76
    Found 12-bit comparator greater for signal <vcnt[11]_GND_16_o_LessThan_10_o> created at line 86
    Found 12-bit comparator lessequal for signal <n0015> created at line 93
    Found 12-bit comparator greater for signal <vcnt[11]_GND_16_o_LessThan_16_o> created at line 93
    Found 12-bit comparator lessequal for signal <n0021> created at line 100
    Found 12-bit comparator lessequal for signal <n0023> created at line 100
    Found 12-bit comparator greater for signal <GND_16_o_vcnt[11]_LessThan_21_o> created at line 115
    Found 12-bit comparator greater for signal <vcnt[11]_GND_16_o_LessThan_22_o> created at line 115
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_23_o> created at line 126
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_24_o> created at line 126
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_25_o> created at line 128
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_26_o> created at line 128
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_27_o> created at line 130
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_28_o> created at line 130
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_29_o> created at line 132
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_30_o> created at line 132
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_31_o> created at line 134
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_32_o> created at line 134
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_33_o> created at line 136
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_34_o> created at line 136
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_35_o> created at line 138
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_36_o> created at line 138
    Found 12-bit comparator greater for signal <GND_16_o_hcnt[11]_LessThan_37_o> created at line 140
    Found 12-bit comparator greater for signal <hcnt[11]_GND_16_o_LessThan_38_o> created at line 140
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  59 D-type flip-flop(s).
	inferred  26 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <vga_module> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 16x4-bit single-port Read Only RAM                    : 1
 4x4-bit single-port Read Only RAM                     : 1
# Adders/Subtractors                                   : 15
 12-bit adder                                          : 2
 16-bit adder                                          : 3
 3-bit adder                                           : 1
 32-bit adder                                          : 5
 4-bit adder                                           : 2
 6-bit adder                                           : 1
 7-bit adder                                           : 1
# Registers                                            : 44
 1-bit register                                        : 10
 12-bit register                                       : 2
 16-bit register                                       : 6
 3-bit register                                        : 2
 32-bit register                                       : 10
 4-bit register                                        : 8
 6-bit register                                        : 1
 7-bit register                                        : 2
 8-bit register                                        : 3
# Comparators                                          : 26
 12-bit comparator greater                             : 22
 12-bit comparator lessequal                           : 4
# Multiplexers                                         : 18
 1-bit 2-to-1 multiplexer                              : 1
 16-bit 2-to-1 multiplexer                             : 10
 32-bit 2-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 1
 6-bit 2-to-1 multiplexer                              : 4
 7-bit 4-to-1 multiplexer                              : 1
# Tristates                                            : 5
 1-bit tristate buffer                                 : 5
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:2261 - The FF/Latch <IR_code_0> in Unit <ir_ct> is equivalent to the following 13 FFs/Latches, which will be removed : <IR_code_1> <IR_code_2> <IR_code_3> <IR_code_4> <IR_code_5> <IR_code_6> <IR_code_7> <IR_code_8> <IR_code_9> <IR_code_12> <IR_code_13> <IR_code_14> <IR_code_15> 
WARNING:Xst:1710 - FF/Latch <IR_code_0> (without init value) has a constant value of 0 in block <ir_ct>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <IR_Value_31> of sequential type is unconnected in block <ir_ct>.
WARNING:Xst:2404 -  FFs/Latches <IR_code<15:12>> (without init value) have a constant value of 0 in block <ir_module>.

Synthesizing (advanced) Unit <ad_module>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <ad_module> synthesized (advanced).

Synthesizing (advanced) Unit <beep_module>.
The following registers are absorbed into counter <cnt_khz>: 1 register on signal <cnt_khz>.
Unit <beep_module> synthesized (advanced).

Synthesizing (advanced) Unit <dt_module>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
INFO:Xst:3231 - The small RAM <Mram_ds_en[3]_num4[3]_mux_23_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 4-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cnt>           |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <dt_module> synthesized (advanced).

Synthesizing (advanced) Unit <ir_module>.
The following registers are absorbed into counter <cnt_l>: 1 register on signal <cnt_l>.
The following registers are absorbed into counter <cnt_val>: 1 register on signal <cnt_val>.
The following registers are absorbed into counter <cnt_h>: 1 register on signal <cnt_h>.
Unit <ir_module> synthesized (advanced).

Synthesizing (advanced) Unit <key_module>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <key_module> synthesized (advanced).

Synthesizing (advanced) Unit <led_module>.
The following registers are absorbed into counter <cnt1>: 1 register on signal <cnt1>.
INFO:Xst:3231 - The small RAM <Mram_PWR_5_o_PWR_5_o_mux_16_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 4-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <led_reg>       |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <led_module> synthesized (advanced).

Synthesizing (advanced) Unit <top>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
The following registers are absorbed into counter <cnt_5m12>: 1 register on signal <cnt_5m12>.
The following registers are absorbed into counter <cnt_16m>: 1 register on signal <cnt_16m>.
The following registers are absorbed into counter <cnt_5k>: 1 register on signal <cnt_5k>.
Unit <top> synthesized (advanced).

Synthesizing (advanced) Unit <vga_module>.
The following registers are absorbed into counter <hcnt>: 1 register on signal <hcnt>.
The following registers are absorbed into counter <vcnt>: 1 register on signal <vcnt>.
Unit <vga_module> synthesized (advanced).
WARNING:Xst:2677 - Node <IR_Value_31> of sequential type is unconnected in block <ir_module>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 16x4-bit single-port distributed Read Only RAM        : 1
 4x4-bit single-port distributed Read Only RAM         : 1
# Adders/Subtractors                                   : 2
 32-bit adder                                          : 1
 6-bit adder                                           : 1
# Counters                                             : 14
 12-bit up counter                                     : 2
 16-bit up counter                                     : 3
 3-bit up counter                                      : 1
 32-bit up counter                                     : 5
 4-bit up counter                                      : 2
 7-bit up counter                                      : 1
# Registers                                            : 277
 Flip-Flops                                            : 277
# Comparators                                          : 26
 12-bit comparator greater                             : 22
 12-bit comparator lessequal                           : 4
# Multiplexers                                         : 15
 1-bit 2-to-1 multiplexer                              : 1
 16-bit 2-to-1 multiplexer                             : 8
 32-bit 2-to-1 multiplexer                             : 1
 6-bit 2-to-1 multiplexer                              : 4
 7-bit 4-to-1 multiplexer                              : 1
# FSMs                                                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <IR_code_0> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_1> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_2> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_3> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_4> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_5> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_6> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_7> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_8> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IR_code_9> (without init value) has a constant value of 0 in block <ir_module>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2146 - In block <top>, Counter <cnt_5m12> <cnt_16m> are equivalent, XST will keep only <cnt_5m12>.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <ir_ct/FSM_2> on signal <state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 011   | 01
 001   | 11
-------------------
WARNING:Xst:2677 - Node <IR_Value_16> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_17> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_18> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_19> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_20> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_21> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_22> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_23> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_24> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_25> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_26> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_27> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_28> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_29> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <IR_Value_30> of sequential type is unconnected in block <ir_module>.
WARNING:Xst:2677 - Node <cnt_17> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_18> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_19> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_20> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_21> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_22> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_23> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_24> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_25> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_26> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_27> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_28> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_29> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_30> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_31> of sequential type is unconnected in block <dt_module>.
WARNING:Xst:2677 - Node <cnt_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cnt_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cnt_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cnt_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cnt_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <cnt_31> of sequential type is unconnected in block <top>.
INFO:Xst:1901 - Instance pll_inst/pll_base_inst in unit pll_inst/pll_base_inst of type PLL_BASE has been replaced by PLL_ADV

Optimizing unit <top> ...

Optimizing unit <ir_module> ...

Optimizing unit <ad_module> ...

Optimizing unit <key_module> ...

Optimizing unit <dt_module> ...
INFO:Xst:2261 - The FF/Latch <cnt_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_0> 
INFO:Xst:2261 - The FF/Latch <cnt_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_1> 
INFO:Xst:2261 - The FF/Latch <cnt_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_2> 
INFO:Xst:2261 - The FF/Latch <cnt_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_3> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_0> 
INFO:Xst:2261 - The FF/Latch <cnt_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_4> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_1> 
INFO:Xst:2261 - The FF/Latch <cnt_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_5> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_2> 
INFO:Xst:2261 - The FF/Latch <cnt_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_6> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_3> 
INFO:Xst:2261 - The FF/Latch <cnt_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_7> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_4> 
INFO:Xst:2261 - The FF/Latch <cnt_8> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_8> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_5> 
INFO:Xst:2261 - The FF/Latch <cnt_9> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_9> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_6> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_7> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_8> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_8> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_9> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_9> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_10> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_10> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_11> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_11> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_12> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_12> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_13> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_13> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_14> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_14> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_20> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_20> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_15> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_15> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_21> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_21> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_16> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_16> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_22> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_22> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_17> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_17> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_23> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_23> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_18> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_18> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_24> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_24> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_19> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_19> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_30> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_30> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_25> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_25> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_31> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_31> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_26> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_26> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_27> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_27> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_28> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_28> 
INFO:Xst:2261 - The FF/Latch <beep_ct/cnt_khz_29> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/cnt_29> 
INFO:Xst:2261 - The FF/Latch <beep_ct/clk_1k> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <key_ct/clk_khz> 
INFO:Xst:2261 - The FF/Latch <cnt_10> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_10> 
INFO:Xst:2261 - The FF/Latch <cnt_11> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_11> 
INFO:Xst:2261 - The FF/Latch <cnt_12> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_12> 
INFO:Xst:2261 - The FF/Latch <cnt_13> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_13> 
INFO:Xst:2261 - The FF/Latch <cnt_14> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_14> 
INFO:Xst:2261 - The FF/Latch <cnt_15> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_15> 
INFO:Xst:2261 - The FF/Latch <cnt_16> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <dt_ct/cnt_16> 

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 12.

Final Macro Processing ...

Processing Unit <top> :
	Found 8-bit shift register for signal <ir_ct/IR_Value_8>.
Unit <top> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 421
 Flip-Flops                                            : 421
# Shift Registers                                      : 1
 8-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 754
#      GND                         : 1
#      INV                         : 17
#      LUT1                        : 149
#      LUT2                        : 23
#      LUT3                        : 43
#      LUT4                        : 41
#      LUT5                        : 23
#      LUT6                        : 103
#      MUXCY                       : 179
#      MUXF7                       : 7
#      VCC                         : 1
#      XORCY                       : 167
# FlipFlops/Latches                : 422
#      FD                          : 222
#      FD_1                        : 2
#      FDC                         : 32
#      FDCE                        : 16
#      FDCE_1                      : 16
#      FDE                         : 41
#      FDR                         : 93
# Shift Registers                  : 1
#      SRLC16E                     : 1
# Clock Buffers                    : 7
#      BUFG                        : 7
# IO Buffers                       : 49
#      IBUF                        : 7
#      IBUFG                       : 1
#      OBUF                        : 40
#      OBUFT                       : 1
# Others                           : 1
#      PLL_ADV                     : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:             422  out of  11440     3%  
 Number of Slice LUTs:                  400  out of   5720     6%  
    Number used as Logic:               399  out of   5720     6%  
    Number used as Memory:                1  out of   1440     0%  
       Number used as SRL:                1

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    582
   Number with an unused Flip Flop:     160  out of    582    27%  
   Number with an unused LUT:           182  out of    582    31%  
   Number of fully used LUT-FF pairs:   240  out of    582    41%  
   Number of unique control sets:        23

IO Utilization: 
 Number of IOs:                          49
 Number of bonded IOBs:                  49  out of    102    48%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                7  out of     16    43%  
 Number of PLL_ADVs:                      1  out of      2    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)        | Load  |
-----------------------------------+------------------------------+-------+
pll_inst/pll_base_inst/CLKOUT0     | BUFG                         | 165   |
led_ct/clk_hz                      | NONE(led_ct/led_reg_3)       | 4     |
vga_ct/hsyncint                    | NONE(vga_ct/vsync)           | 13    |
pll_inst/pll_base_inst/CLKOUT1     | BUFG                         | 7     |
cnt_5m12_6                         | NONE(cnt_5k_0)               | 11    |
cnt_5m12_3                         | BUFG                         | 87    |
ADCLK_OBUF(ad_ct/Mmux_adc_clk11:O) | NONE(*)(ad_ct/adc_data_buf_7)| 8     |
beep_ct/clk_1k                     | BUFG                         | 128   |
-----------------------------------+------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 10.385ns (Maximum Frequency: 96.290MHz)
   Minimum input arrival time before clock: 3.911ns
   Maximum output required time after clock: 6.975ns
   Maximum combinational path delay: 4.372ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'pll_inst/pll_base_inst/CLKOUT0'
  Clock period: 10.385ns (frequency: 96.290MHz)
  Total number of paths / destination ports: 6411 / 249
-------------------------------------------------------------------------
Delay:               5.193ns (Levels of Logic = 4)
  Source:            vga_ct/hcnt_2 (FF)
  Destination:       vga_ct/PColor_14 (FF)
  Source Clock:      pll_inst/pll_base_inst/CLKOUT0 rising
  Destination Clock: pll_inst/pll_base_inst/CLKOUT0 falling

  Data Path: vga_ct/hcnt_2 to vga_ct/PColor_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   0.447   1.302  vga_ct/hcnt_2 (vga_ct/hcnt_2)
     LUT6:I1->O            3   0.203   0.651  vga_ct/GND_16_o_hcnt[11]_AND_22_o1 (vga_ct/GND_16_o_hcnt[11]_AND_22_o1)
     LUT6:I5->O            6   0.205   1.089  vga_ct/GND_16_o_hcnt[11]_AND_22_o2 (vga_ct/GND_16_o_hcnt[11]_AND_22_o)
     LUT6:I1->O            4   0.203   0.788  vga_ct/Mmux_GND_16_o_PColor[15]_mux_45_OUT1011 (vga_ct/Mmux_GND_16_o_PColor[15]_mux_45_OUT101)
     LUT3:I1->O            1   0.203   0.000  vga_ct/Mmux_GND_16_o_PColor[15]_mux_45_OUT101 (vga_ct/GND_16_o_PColor[15]_mux_45_OUT<13>)
     FDCE_1:D                  0.102          vga_ct/PColor_13
    ----------------------------------------
    Total                      5.193ns (1.363ns logic, 3.830ns route)
                                       (26.2% logic, 73.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'led_ct/clk_hz'
  Clock period: 1.714ns (frequency: 583.431MHz)
  Total number of paths / destination ports: 16 / 4
-------------------------------------------------------------------------
Delay:               1.714ns (Levels of Logic = 1)
  Source:            led_ct/led_reg_2 (FF)
  Destination:       led_ct/led_reg_3 (FF)
  Source Clock:      led_ct/clk_hz rising
  Destination Clock: led_ct/clk_hz rising

  Data Path: led_ct/led_reg_2 to led_ct/led_reg_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.962  led_ct/led_reg_2 (led_ct/led_reg_2)
     LUT4:I0->O            1   0.203   0.000  led_ct/Mram_PWR_5_o_PWR_5_o_mux_16_OUT31 (led_ct/Mram_PWR_5_o_PWR_5_o_mux_16_OUT3)
     FD:D                      0.102          led_ct/led_reg_3
    ----------------------------------------
    Total                      1.714ns (0.752ns logic, 0.962ns route)
                                       (43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'vga_ct/hsyncint'
  Clock period: 4.060ns (frequency: 246.327MHz)
  Total number of paths / destination ports: 210 / 25
-------------------------------------------------------------------------
Delay:               4.060ns (Levels of Logic = 2)
  Source:            vga_ct/vcnt_5 (FF)
  Destination:       vga_ct/vcnt_0 (FF)
  Source Clock:      vga_ct/hsyncint rising
  Destination Clock: vga_ct/hsyncint rising

  Data Path: vga_ct/vcnt_5 to vga_ct/vcnt_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.447   1.059  vga_ct/vcnt_5 (vga_ct/vcnt_5)
     LUT5:I0->O            1   0.203   0.808  vga_ct/vcnt[11]_GND_16_o_LessThan_10_o_inv1 (vga_ct/vcnt[11]_GND_16_o_LessThan_10_o_inv1)
     LUT6:I3->O           12   0.205   0.908  vga_ct/vcnt[11]_GND_16_o_LessThan_10_o_inv2 (vga_ct/vcnt[11]_GND_16_o_LessThan_10_o_inv)
     FDR:R                     0.430          vga_ct/vcnt_0
    ----------------------------------------
    Total                      4.060ns (1.285ns logic, 2.775ns route)
                                       (31.7% logic, 68.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'pll_inst/pll_base_inst/CLKOUT1'
  Clock period: 2.727ns (frequency: 366.723MHz)
  Total number of paths / destination ports: 28 / 7
-------------------------------------------------------------------------
Delay:               2.727ns (Levels of Logic = 2)
  Source:            cnt_5m12_2 (FF)
  Destination:       cnt_5m12_6 (FF)
  Source Clock:      pll_inst/pll_base_inst/CLKOUT1 rising
  Destination Clock: pll_inst/pll_base_inst/CLKOUT1 rising

  Data Path: cnt_5m12_2 to cnt_5m12_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.943  cnt_5m12_2 (cnt_5m12_2)
     LUT3:I0->O            1   0.205   0.827  Mcount_cnt_5m12_xor<3>111 (Mcount_cnt_5m12_xor<3>11)
     LUT5:I1->O            1   0.203   0.000  Mcount_cnt_5m12_xor<6>11 (Result<6>1)
     FD:D                      0.102          cnt_5m12_6
    ----------------------------------------
    Total                      2.727ns (0.957ns logic, 1.770ns route)
                                       (35.1% logic, 64.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cnt_5m12_6'
  Clock period: 1.984ns (frequency: 504.007MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               1.984ns (Levels of Logic = 1)
  Source:            cnt_5k_0 (FF)
  Destination:       cnt_5k_0 (FF)
  Source Clock:      cnt_5m12_6 rising
  Destination Clock: cnt_5m12_6 rising

  Data Path: cnt_5k_0 to cnt_5k_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.447   0.650  cnt_5k_0 (cnt_5k_0)
     INV:I->O              1   0.206   0.579  Mcount_cnt_5k_xor<0>11_INV_0 (Result<0>6)
     FD:D                      0.102          cnt_5k_0
    ----------------------------------------
    Total                      1.984ns (0.755ns logic, 1.229ns route)
                                       (38.1% logic, 61.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cnt_5m12_3'
  Clock period: 7.431ns (frequency: 134.568MHz)
  Total number of paths / destination ports: 1504 / 144
-------------------------------------------------------------------------
Delay:               3.716ns (Levels of Logic = 3)
  Source:            ir_ct/cnt_l_10 (FF)
  Destination:       ir_ct/Flag_LVL (FF)
  Source Clock:      cnt_5m12_3 rising
  Destination Clock: cnt_5m12_3 falling

  Data Path: ir_ct/cnt_l_10 to ir_ct/Flag_LVL
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             18   0.447   1.050  ir_ct/cnt_l_10 (ir_ct/cnt_l_10)
     LUT6:I5->O            1   0.205   0.924  ir_ct/cnt_l[15]_GND_14_o_equal_15_o<15>2 (ir_ct/cnt_l[15]_GND_14_o_equal_15_o<15>1)
     LUT6:I1->O            1   0.203   0.580  ir_ct/cnt_l[15]_GND_14_o_equal_15_o<15>3 (ir_ct/cnt_l[15]_GND_14_o_equal_15_o)
     LUT4:I3->O            1   0.205   0.000  ir_ct/Flag_LVL_rstpot (ir_ct/Flag_LVL_rstpot)
     FD_1:D                    0.102          ir_ct/Flag_LVL
    ----------------------------------------
    Total                      3.716ns (1.162ns logic, 2.554ns route)
                                       (31.3% logic, 68.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'ADCLK_OBUF'
  Clock period: 1.165ns (frequency: 858.185MHz)
  Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay:               1.165ns (Levels of Logic = 0)
  Source:            ad_ct/adc_data_buf_7 (FF)
  Destination:       ad_ct/adc_data_buf_6 (FF)
  Source Clock:      ADCLK_OBUF rising
  Destination Clock: ADCLK_OBUF rising

  Data Path: ad_ct/adc_data_buf_7 to ad_ct/adc_data_buf_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.447   0.616  ad_ct/adc_data_buf_7 (ad_ct/adc_data_buf_7)
     FDE:D                     0.102          ad_ct/adc_data_buf_6
    ----------------------------------------
    Total                      1.165ns (0.549ns logic, 0.616ns route)
                                       (47.1% logic, 52.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'beep_ct/clk_1k'
  Clock period: 1.165ns (frequency: 858.185MHz)
  Total number of paths / destination ports: 124 / 124
-------------------------------------------------------------------------
Delay:               1.165ns (Levels of Logic = 0)
  Source:            key_ct/key_reg3_30 (FF)
  Destination:       key_ct/key_reg3_31 (FF)
  Source Clock:      beep_ct/clk_1k rising
  Destination Clock: beep_ct/clk_1k rising

  Data Path: key_ct/key_reg3_30 to key_ct/key_reg3_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.447   0.616  key_ct/key_reg3_30 (key_ct/key_reg3_30)
     FD:D                      0.102          key_ct/key_reg3_31
    ----------------------------------------
    Total                      1.165ns (0.549ns logic, 0.616ns route)
                                       (47.1% logic, 52.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cnt_5m12_3'
  Total number of paths / destination ports: 33 / 33
-------------------------------------------------------------------------
Offset:              3.911ns (Levels of Logic = 2)
  Source:            IRDA (PAD)
  Destination:       ir_ct/cnt_h_15 (FF)
  Destination Clock: cnt_5m12_3 rising

  Data Path: IRDA to ir_ct/cnt_h_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            18   1.222   1.049  IRDA_IBUF (IRDA_IBUF)
     INV:I->O             16   0.206   1.004  ir_ct/ir_inv1_INV_0 (ir_ct/ir_inv)
     FDC:CLR                   0.430          ir_ct/cnt_h_0
    ----------------------------------------
    Total                      3.911ns (1.858ns logic, 2.053ns route)
                                       (47.5% logic, 52.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'ADCLK_OBUF'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.903ns (Levels of Logic = 1)
  Source:            ADDAT (PAD)
  Destination:       ad_ct/adc_data_buf_7 (FF)
  Destination Clock: ADCLK_OBUF rising

  Data Path: ADDAT to ad_ct/adc_data_buf_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  ADDAT_IBUF (ADDAT_IBUF)
     FDE:D                     0.102          ad_ct/adc_data_buf_7
    ----------------------------------------
    Total                      1.903ns (1.324ns logic, 0.579ns route)
                                       (69.6% logic, 30.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'beep_ct/clk_1k'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              2.688ns (Levels of Logic = 2)
  Source:            KEY4 (PAD)
  Destination:       key_ct/key_reg3_0 (FF)
  Destination Clock: beep_ct/clk_1k rising

  Data Path: KEY4 to key_ct/key_reg3_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  KEY4_IBUF (KEY4_IBUF)
     INV:I->O              1   0.206   0.579  key_ct/key[3]_INV_11_o1_INV_0 (key_ct/key[3]_INV_11_o)
     FD:D                      0.102          key_ct/key_reg3_0
    ----------------------------------------
    Total                      2.688ns (1.530ns logic, 1.158ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'led_ct/clk_hz'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              3.732ns (Levels of Logic = 1)
  Source:            led_ct/led_reg_3 (FF)
  Destination:       LED<3> (PAD)
  Source Clock:      led_ct/clk_hz rising

  Data Path: led_ct/led_reg_3 to LED<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.714  led_ct/led_reg_3 (led_ct/led_reg_3)
     OBUF:I->O                 2.571          LED_3_OBUF (LED<3>)
    ----------------------------------------
    Total                      3.732ns (3.018ns logic, 0.714ns route)
                                       (80.9% logic, 19.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'pll_inst/pll_base_inst/CLKOUT0'
  Total number of paths / destination ports: 30 / 30
-------------------------------------------------------------------------
Offset:              3.975ns (Levels of Logic = 1)
  Source:            vga_ct/hsyncint (FF)
  Destination:       H_SYNC (PAD)
  Source Clock:      pll_inst/pll_base_inst/CLKOUT0 rising

  Data Path: vga_ct/hsyncint to H_SYNC
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              14   0.447   0.957  vga_ct/hsyncint (vga_ct/hsyncint)
     OBUF:I->O                 2.571          H_SYNC_OBUF (H_SYNC)
    ----------------------------------------
    Total                      3.975ns (3.018ns logic, 0.957ns route)
                                       (75.9% logic, 24.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'beep_ct/clk_1k'
  Total number of paths / destination ports: 128 / 1
-------------------------------------------------------------------------
Offset:              6.975ns (Levels of Logic = 4)
  Source:            key_ct/key_reg2_3 (FF)
  Destination:       BP1 (PAD)
  Source Clock:      beep_ct/clk_1k rising

  Data Path: key_ct/key_reg2_3 to BP1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.447   0.981  key_ct/key_reg2_3 (key_ct/key_reg2_3)
     LUT6:I0->O            1   0.203   0.924  key_ct/key_flag<2><31>6 (key_ct/key_flag<2><31>5)
     LUT6:I1->O            2   0.203   0.864  key_ct/key_flag<2><31>7 (key_value<2>)
     LUT4:I0->O            1   0.203   0.579  beep_ct/en_inv1 (beep_ct/en_inv)
     OBUFT:T->O                2.571          BP1_OBUFT (BP1)
    ----------------------------------------
    Total                      6.975ns (3.627ns logic, 3.348ns route)
                                       (52.0% logic, 48.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cnt_5m12_3'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              4.734ns (Levels of Logic = 2)
  Source:            ad_ct/adc_clk_valid (FF)
  Destination:       ADCLK (PAD)
  Source Clock:      cnt_5m12_3 rising

  Data Path: ad_ct/adc_clk_valid to ADCLK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.447   0.684  ad_ct/adc_clk_valid (ad_ct/adc_clk_valid)
     LUT2:I0->O            9   0.203   0.829  ad_ct/Mmux_adc_clk11 (ADCLK_OBUF)
     OBUF:I->O                 2.571          ADCLK_OBUF (ADCLK)
    ----------------------------------------
    Total                      4.734ns (3.221ns logic, 1.513ns route)
                                       (68.0% logic, 32.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'pll_inst/pll_base_inst/CLKOUT1'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.767ns (Levels of Logic = 2)
  Source:            cnt_5m12_3 (FF)
  Destination:       ADCLK (PAD)
  Source Clock:      pll_inst/pll_base_inst/CLKOUT1 rising

  Data Path: cnt_5m12_3 to ADCLK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.715  cnt_5m12_3 (cnt_5m12_3)
     LUT2:I1->O            9   0.205   0.829  ad_ct/Mmux_adc_clk11 (ADCLK_OBUF)
     OBUF:I->O                 2.571          ADCLK_OBUF (ADCLK)
    ----------------------------------------
    Total                      4.767ns (3.223ns logic, 1.544ns route)
                                       (67.6% logic, 32.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'vga_ct/hsyncint'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.597ns (Levels of Logic = 1)
  Source:            vga_ct/vsync (FF)
  Destination:       V_SYNC (PAD)
  Source Clock:      vga_ct/hsyncint rising

  Data Path: vga_ct/vsync to V_SYNC
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.447   0.579  vga_ct/vsync (vga_ct/vsync)
     OBUF:I->O                 2.571          V_SYNC_OBUF (V_SYNC)
    ----------------------------------------
    Total                      3.597ns (3.018ns logic, 0.579ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cnt_5m12_6'
  Total number of paths / destination ports: 10 / 3
-------------------------------------------------------------------------
Offset:              5.395ns (Levels of Logic = 3)
  Source:            ad_ct/adc_data_7 (FF)
  Destination:       DNC (PAD)
  Source Clock:      cnt_5m12_6 rising

  Data Path: ad_ct/adc_data_7 to DNC
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.447   0.808  ad_ct/adc_data_7 (ad_ct/adc_data_7)
     LUT3:I0->O            1   0.205   0.580  DNC<7>_SW0 (N01)
     LUT6:I5->O            1   0.205   0.579  DNC<7> (DNC_OBUF)
     OBUF:I->O                 2.571          DNC_OBUF (DNC)
    ----------------------------------------
    Total                      5.395ns (3.428ns logic, 1.967ns route)
                                       (63.5% logic, 36.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               4.372ns (Levels of Logic = 2)
  Source:            TXD (PAD)
  Destination:       RXD (PAD)

  Data Path: TXD to RXD
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  TXD_IBUF (RXD_OBUF)
     OBUF:I->O                 2.571          RXD_OBUF (RXD)
    ----------------------------------------
    Total                      4.372ns (3.793ns logic, 0.579ns route)
                                       (86.8% logic, 13.2% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock ADCLK_OBUF
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ADCLK_OBUF     |    1.165|         |         |         |
cnt_5m12_3     |    2.393|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock beep_ct/clk_1k
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
beep_ct/clk_1k |    1.165|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock cnt_5m12_3
------------------------------+---------+---------+---------+---------+
                              | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                  |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------------------+---------+---------+---------+---------+
cnt_5m12_3                    |    4.818|    3.325|    3.716|         |
pll_inst/pll_base_inst/CLKOUT1|    2.698|         |         |         |
------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cnt_5m12_6
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ADCLK_OBUF     |    1.165|         |         |         |
cnt_5m12_6     |    1.984|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock led_ct/clk_hz
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
led_ct/clk_hz  |    1.714|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock pll_inst/pll_base_inst/CLKOUT0
------------------------------+---------+---------+---------+---------+
                              | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                  |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------------------+---------+---------+---------+---------+
beep_ct/clk_1k                |    4.957|         |         |         |
cnt_5m12_3                    |    1.128|         |         |         |
pll_inst/pll_base_inst/CLKOUT0|    5.188|    1.165|    5.193|         |
vga_ct/hsyncint               |    3.874|         |    4.625|         |
------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock pll_inst/pll_base_inst/CLKOUT1
------------------------------+---------+---------+---------+---------+
                              | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                  |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------------------+---------+---------+---------+---------+
pll_inst/pll_base_inst/CLKOUT1|    2.727|         |         |         |
------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock vga_ct/hsyncint
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
vga_ct/hsyncint|    4.060|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.81 secs
 
--> 

Total memory usage is 261072 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   59 (   0 filtered)
Number of infos    :   58 (   0 filtered)

