Xilinx Design Summary

top Project Status (06/20/2014 - 23:51:37)
Project File: | top.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Programming File Generated

Target Device:

xc6slx9-3tqg144

- Errors:

No Errors

Product Version:

ISE 14.7

- Warnings:

19 Warnings (0 new)

Design Goal:

Balanced

- Routing Results:

All Signals Completely Routed

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

All Constraints Met

Environment:

System Settings

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 271 | 11,440 | 2% |
Number used as Flip Flops | 271 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 336 | 5,720 | 5% |
Number used as logic | 283 | 5,720 | 4% |
Number using O6 output only | 139 |  |  |
Number using O5 output only | 129 |  |  |
Number using O5 and O6 | 15 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 0 | 1,440 | 0% |
Number used exclusively as route-thrus | 53 |  |  |
Number with same-slice register load | 48 |  |  |
Number with same-slice carry load | 5 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 105 | 1,430 | 7% |
Number of MUXCYs used | 148 | 2,860 | 5% |
Number of LUT Flip Flop pairs used | 355 |  |  |
Number with an unused Flip Flop | 136 | 355 | 38% |
Number with an unused LUT | 19 | 355 | 5% |
Number of fully used LUT-FF pairs | 200 | 355 | 56% |
Number of unique control sets | 3 |  |  |
Number of slice register sites lost to control set restrictions | 9 | 11,440 | 1% |
Number of bonded IOBs | 20 | 102 | 19% |
Number of LOCed IOBs | 20 | 20 | 100% |
Number of RAMB16BWERs | 0 | 32 | 0% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 2.05 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周五 六月 20 23:50:35 2014 | 0 | 18 Warnings (0 new) | 3 Infos (0 new)
Translation Report | Current | 周五 六月 20 23:50:43 2014 | 0 | 0 | 0
Map Report | Current | 周五 六月 20 23:50:56 2014 | 0 | 1 Warning (0 new) | 7 Infos (0 new)
Place and Route Report | Current | 周五 六月 20 23:51:07 2014 | 0 | 0 | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | 周五 六月 20 23:51:14 2014 | 0 | 0 | 4 Infos (0 new)
Bitgen Report | Current | 周五 六月 20 23:51:25 2014 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | 周五 六月 20 23:51:26 2014
WebTalk Log File | Current | 周五 六月 20 23:51:37 2014

Date Generated: 06/20/2014 -