Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Sat Jun 21 00:01:45 2014

All signals are completely routed.

WARNING:ParHelpers:361 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   KEY2_IBUF
   KEY3_IBUF


