Device Usage Statistics Report

### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.

Software Version and Target Device
Product Version: | ISE:14.7 (WebPack) - P.20131013 | Target Family: | Virtex4
OS Platform: | NT64 | Target Device: | xc4vsx25
Project ID (random number) | 9af4f16000124bd594554d52cdb242aa. 0943426544E5F543D632A45EB495A4BC. 1 | Target Package: | ff668
Registration ID | __0_0_0 | Target Speed: | -12
Date Generated | 2014-06-10T23:54:00 | Tool Flow | ISE

User Environment
OS Name | Microsoft Windows 7 , 64-bit | OS Release | Service Pack 1 (build 7601)
CPU Name | AMD A8-5600K APU with Radeon(tm) HD Graphics | CPU Speed | 3600 MHz

Device Usage Statistics
Macro Statistics | Miscellaneous Statistics | Net Statistics | Site Usage

Adders/Subtractors=5

- 16-bit subtractor=1
- 2-bit subtractor=2
- 3-bit subtractor=1
- 4-bit subtractor=1

ROMs=1

- 4x3-bit ROM=1

Registers=321

- Flip-Flops=321

MiscellaneousStatistics

- AGG_BONDED_IO=92
- AGG_IO=92
- AGG_SLICE=230
- NUM_4_INPUT_LUT=173
- NUM_BONDED_IOB=92
- NUM_BUFG=2
- NUM_CYMUX=15
- NUM_DCM_ADV=2
- NUM_LUT_RT=5
- NUM_SHIFT=34
- NUM_SLICEL=196
- NUM_SLICEM=34
- NUM_SLICE_FF=293
- NUM_XOR=16

NetStatistics

- NumNets_Active=576
- NumNets_Gnd=1
- NumNets_Vcc=1
- NumNodesOfType_Active_BOUNCEIN=162
- NumNodesOfType_Active_BUFGOUT=2
- NumNodesOfType_Active_CLKPIN=214
- NumNodesOfType_Active_CNTRLPIN=212
- NumNodesOfType_Active_DOUBLE=1027
- NumNodesOfType_Active_GENERIC=10
- NumNodesOfType_Active_GLOBAL=61
- NumNodesOfType_Active_HLONG=3
- NumNodesOfType_Active_HUNIHEX=102
- NumNodesOfType_Active_INPUT=671
- NumNodesOfType_Active_IOBIN2OUT=69
- NumNodesOfType_Active_IOBINPUT=144
- NumNodesOfType_Active_IOBOUTPUT=213
- NumNodesOfType_Active_OMUX=478
- NumNodesOfType_Active_OUTBOUND=469
- NumNodesOfType_Active_OUTPUT=413
- NumNodesOfType_Active_PADINPUT=144
- NumNodesOfType_Active_PADOUTPUT=69
- NumNodesOfType_Active_PINBOUNCE=402
- NumNodesOfType_Active_PINFEED=946
- NumNodesOfType_Active_VLONG=9
- NumNodesOfType_Active_VUNIHEX=189
- NumNodesOfType_Vcc_CNTRLPIN=34
- NumNodesOfType_Vcc_HVCCOUT=25
- NumNodesOfType_Vcc_INPUT=73
- NumNodesOfType_Vcc_IOBINPUT=1
- NumNodesOfType_Vcc_IOBOUTPUT=1
- NumNodesOfType_Vcc_KVCCOUT=29
- NumNodesOfType_Vcc_PADINPUT=1
- NumNodesOfType_Vcc_PINBOUNCE=2
- NumNodesOfType_Vcc_PINFEED=106

SiteStatistics

- BUFG-BUFGCTRL=2
- IOB-IOBM=37
- IOB-IOBS=41
- IOB-LOWCAPIOB=14
- SLICEL-SLICEM=104

SiteSummary

- BUFG=2
- BUFG_GCLK_BUFFER=2
- DCM_ADV=4
- DCM_ADV_DCM_ADV=4
- IOB=92
- IOB_INBUF=69
- IOB_OUTBUF=87
- IOB_PAD=92
- PMV=1
- PMV_PMV=1
- SLICEL=196
- SLICEL_C1VDD=7
- SLICEL_C2VDD=7
- SLICEL_CYMUXF=8
- SLICEL_CYMUXG=7
- SLICEL_F=70
- SLICEL_F5MUX=8
- SLICEL_FFX=136
- SLICEL_FFY=157
- SLICEL_G=69
- SLICEL_GNDF=1
- SLICEL_XORF=8
- SLICEL_XORG=8
- SLICEM=34
- SLICEM_G=34
- SLICEM_WSGEN=34

Configuration Data

DCM_ADV

- CTLMODE=[CTLMODE:2] [CTLMODE_INV:0]
- PSEN=[PSEN_INV:2] [PSEN:2]
- PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
- RST=[RST:2] [RST_INV:0]

DCM_ADV_DCM_ADV

- BGM_CONFIG_REF_SEL=[CLKIN:4]
- BGM_DIVIDE=[16:4]
- BGM_LDLY=[5:4]
- BGM_MODE=[BG_SNAPSHOT:4]
- BGM_MULTIPLY=[16:4]
- BGM_SAMPLE_LEN=[2:4]
- BGM_SDLY=[3:4]
- BGM_VADJ=[5:4]
- BGM_VLDLY=[7:4]
- BGM_VSDLY=[0:4]
- CLKDV_DIVIDE=[2.0:4]
- CLKFX_DIVIDE=[1:4]
- CLKFX_MULTIPLY=[4:4]
- CLKIN_DIVIDE_BY_2=[FALSE:2] [TRUE:2]
- CLKOUT_PHASE_SHIFT=[FIXED:4]
- CLK_FEEDBACK=[1X:4]
- CTLMODE=[CTLMODE:2] [CTLMODE_INV:0]
- DCM_CLKDV_CLKFX_ALIGNMENT=[TRUE:4]
- DCM_EXT_FB_EN=[FALSE:4]
- DCM_LOCK_HIGH=[FALSE:4]
- DCM_PERFORMANCE_MODE=[MAX_SPEED:4]
- DCM_UNUSED_TAPS_POWERDOWN=[FALSE:2] [TRUE:2]
- DCM_VREF_SOURCE=[VBG_DLL:4]
- DCM_VREG_ENABLE=[FALSE:2] [TRUE:2]
- DESKEW_ADJUST=[17:4]
- DFS_AVE_FREQ_ADJ_INTERVAL=[3:4]
- DFS_AVE_FREQ_GAIN=[2.0:4]
- DFS_AVE_FREQ_SAMPLE_INTERVAL=[2:4]
- DFS_COARSE_SEL=[LEGACY:4]
- DFS_EARLY_LOCK=[FALSE:4]
- DFS_EN_RELRST=[TRUE:4]
- DFS_EXTEND_FLUSH_TIME=[FALSE:4]
- DFS_EXTEND_HALT_TIME=[FALSE:4]
- DFS_EXTEND_RUN_TIME=[FALSE:4]
- DFS_FINE_SEL=[LEGACY:4]
- DFS_FREQUENCY_MODE=[LOW:4]
- DFS_NON_STOP=[FALSE:4]
- DFS_OSCILLATOR_MODE=[PHASE_FREQ_LOCK:4]
- DFS_SKIP_FINE=[FALSE:4]
- DFS_TP_SEL=[LEVEL:4]
- DFS_TRACKMODE=[1:4]
- DLL_CONTROL_CLOCK_SPEED=[HALF:4]
- DLL_CTL_SEL_CLKIN_DIV2=[FALSE:4]
- DLL_DESKEW_LOCK_BY1=[FALSE:4]
- DLL_FREQUENCY_MODE=[LOW:4]
- DLL_PD_DLY_SEL=[0:4]
- DLL_PERIOD_LOCK_BY1=[FALSE:4]
- DLL_PHASE_DETECTOR_AUTO_RESET=[TRUE:4]
- DLL_PHASE_DETECTOR_MODE=[ENHANCED:4]
- DLL_PHASE_SHIFT_CALIBRATION=[AUTO_DPS:4]
- DLL_PHASE_SHIFT_LOCK_BY1=[FALSE:4]
- DUTY_CYCLE_CORRECTION=[TRUE:4]
- PMCD_SYNC=[FALSE:4]
- PSEN=[PSEN_INV:2] [PSEN:2]
- PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
- RST=[RST:2] [RST_INV:0]
- STARTUP_WAIT=[FALSE:4]

IOB_PAD

- DRIVEATTRBOX=[12:86] [16:1]
- IOATTRBOX=[LVCMOS25:92]
- SLEW=[FAST:87]

SLICEL

- BX=[BX_INV:0] [BX:118]
- BY=[BY:139] [BY_INV:1]
- CE=[CE:31] [CE_INV:10]
- CIN=[CIN_INV:0] [CIN:7]
- CLK=[CLK:172] [CLK_INV:0]
- SR=[SR:18] [SR_INV:153]

SLICEL_CYMUXF

- 0=[0:8] [0_INV:0]
- 1=[1_INV:0] [1:8]

SLICEL_CYMUXG

- 0=[0:7] [0_INV:0]

SLICEL_F5MUX

- S0=[S0:8] [S0_INV:0]

SLICEL_FFX

- CE=[CE:29] [CE_INV:10]
- CK=[CK:136] [CK_INV:0]
- D=[D:136] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:110] [INIT1:26]
- FFX_SR_ATTR=[SRLOW:110] [SRHIGH:26]
- LATCH_OR_FF=[FF:136]
- SR=[SR:1] [SR_INV:135]
- SYNC_ATTR=[ASYNC:135] [SYNC:1]

SLICEL_FFY

- CE=[CE:31] [CE_INV:10]
- CK=[CK:157] [CK_INV:0]
- D=[D:156] [D_INV:1]
- FFY_INIT_ATTR=[INIT0:128] [INIT1:29]
- FFY_SR_ATTR=[SRLOW:128] [SRHIGH:29]
- LATCH_OR_FF=[FF:157]
- REV=[REV_INV:0] [REV:16]
- SR=[SR:18] [SR_INV:138]
- SYNC_ATTR=[ASYNC:155] [SYNC:2]

SLICEL_XORF

- 1=[1_INV:0] [1:8]

SLICEM

- BY=[BY:34] [BY_INV:0]
- CLK=[CLK:34] [CLK_INV:0]
- SR=[SR:34] [SR_INV:0]

SLICEM_G

- DI=[DI:34] [DI_INV:0]
- G_ATTR=[SHIFT_REG:34]
- LUT_OR_MEM=[RAM:34]

SLICEM_WSGEN

- CK=[CK:34] [CK_INV:0]
- WE=[WE_INV:0] [WE:34]

Pin Data

BUFG

- I0=2
- O=2

BUFG_GCLK_BUFFER

- IN=2
- OUT=2

DCM_ADV

- CLK0=4
- CLK2X=1
- CLKFB=4
- CLKIN=4
- CTLMODE=2
- LOCKED=2
- PSEN=4
- PSINCDEC=2
- RST=2

DCM_ADV_DCM_ADV

- CLK0=4
- CLK2X=1
- CLKFB=4
- CLKIN=4
- CTLMODE=2
- LOCKED=2
- PSEN=4
- PSINCDEC=2
- RST=2

IOB

- I=69
- O=87
- PAD=92
- T=64

IOB_INBUF

- OUT=69
- PAD=69

IOB_OUTBUF

- IN=87
- OUT=87
- TRI=64

IOB_PAD

- PAD=92

PMV

- A0=1
- A1=1
- A2=1
- A3=1
- A4=1
- A5=1
- EN=1
- ODIV4=1

PMV_PMV

- A0=1
- A1=1
- A2=1
- A3=1
- A4=1
- A5=1
- EN=1
- ODIV4=1

SLICEL

- BX=118
- BY=140
- CE=41
- CIN=7
- CLK=172
- COUT=7
- F1=69
- F2=57
- F3=28
- F4=21
- G1=69
- G2=61
- G3=46
- G4=19
- SR=171
- X=35
- XMUX=8
- XQ=136
- Y=20
- YMUX=8
- YQ=157

SLICEL_C1VDD

- 1=7

SLICEL_C2VDD

- 1=7

SLICEL_CYMUXF

- 0=8
- 1=8
- OUT=8
- S0=8

SLICEL_CYMUXG

- 0=7
- 1=7
- OUT=7
- S0=7

SLICEL_F

- A1=69
- A2=57
- A3=28
- A4=21
- D=70

SLICEL_F5MUX

- 0=8
- 1=8
- OUT=8
- S0=8

SLICEL_FFX

- CE=39
- CK=136
- D=136
- Q=136
- SR=136

SLICEL_FFY

- CE=41
- CK=157
- D=157
- Q=157
- REV=16
- SR=156

SLICEL_G

- A1=69
- A2=61
- A3=46
- A4=19
- D=69

SLICEL_GNDF

- 0=1

SLICEL_XORF

- 0=8
- 1=8
- O=8

SLICEL_XORG

- 0=8
- 1=8
- O=8

SLICEM

- BY=34
- CLK=34
- G1=34
- G2=34
- G3=34
- G4=34
- SR=34
- Y=34

SLICEM_G

- A1=34
- A2=34
- A3=34
- A4=34
- D=34
- DI=34
- WS=34

SLICEM_WSGEN

- CK=34
- WE=34
- WSG=34

Tool Usage

Command Line History

- xst -intstyle ise -ifn <ise_file>
- ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc4vsx25-ff668-12 <fname>.ngc <fname>.ngd
- map -intstyle ise -p xc4vsx25-ff668-12 -global_opt off -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc4vsx25-ff668-12 <fname>.ngc <fname>.ngd
- map -intstyle ise -p xc4vsx25-ff668-12 -global_opt off -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc4vsx25-ff668-12 <fname>.ngc <fname>.ngd
- map -intstyle ise -p xc4vsx25-ff668-12 -global_opt off -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
- par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
- trce -intstyle ise -v 3 -s 12 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
- bitgen -intstyle ise -f <fname>.ut <fname>.ncd

Software Quality
Run Statistics
Program Name | Runs Started | Runs Finished | Errors | Fatal Errors | Internal Errors | Exceptions | Core Dumps
_impact | 2 | 2 | 0 | 0 | 0 | 0 | 0
bitgen | 2 | 2 | 0 | 0 | 0 | 0 | 0
map | 4 | 2 | 0 | 0 | 0 | 0 | 0
ngdbuild | 6 | 6 | 0 | 0 | 0 | 0 | 0
par | 2 | 2 | 0 | 0 | 0 | 0 | 0
trce | 2 | 2 | 0 | 0 | 0 | 0 | 0
xst | 3 | 3 | 0 | 0 | 0 | 0 | 0

Help Statistics
Help files
/doc/usenglish/isehelp/pim_c_arranging_windows.htm ( 1 ) | /doc/usenglish/isehelp/pim_c_device_configuration.htm ( 1 )
/doc/usenglish/isehelp/pim_c_overview.htm ( 1 ) | /doc/usenglish/isehelp/pim_c_webtalk_in_impact.htm ( 1 )
/doc/usenglish/isehelp/pim_db_impact_wizard.htm ( 1 ) | /doc/usenglish/isehelp/pim_p_accessing_impact_from_command_line_prompt.htm ( 1 )
/doc/usenglish/isehelp/pim_p_creating_a_new_projectfile.htm ( 1 ) | /doc/usenglish/isehelp/pim_p_loading_project_files.htm ( 1 )
/doc/usenglish/isehelp/pim_p_opening_impact_project.htm ( 1 ) | /doc/usenglish/isehelp/pim_r_configurationtabs.htm ( 1 )
/doc/usenglish/isehelp/pim_r_console_comds.htm ( 1 ) | /doc/usenglish/isehelp/pim_r_impactfiles.htm ( 1 )
/doc/usenglish/isehelp/pim_r_short.htm ( 1 ) | /doc/usenglish/isehelp/pim_r_supportedcables.htm ( 1 )
/doc/usenglish/isehelp/pim_r_toolbar.htm ( 1 )

Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2= 100000 | PROP_Enable_Message_Filtering= false
PROP_FitterReportFormat= HTML | PROP_LastAppliedGoal= Balanced
PROP_LastAppliedStrategy= Xilinx Default (unlocked) | PROP_ManualCompileOrderImp= false
PROP_PropSpecInProjFile= Store all values | PROP_Simulator= ISim (VHDL/Verilog)
PROP_SynthTopFile= changed | PROP_Top_Level_Module_Type= HDL
PROP_UseSmartGuide= false | PROP_UserConstraintEditorPreference= Text Editor
PROP_intProjectCreationTimestamp= 2012-03-23T13:09:06 | PROP_intWbtProjectID= 0943426544E5F543D632A45EB495A4BC
PROP_intWbtProjectIteration= 1 | PROP_intWorkingDirLocWRTProjDir= Same
PROP_intWorkingDirUsed= No | PROP_xilxBitgStart_IntDone= true
PROP_AutoTop= false | PROP_CompxlibEdkSimLib= false
PROP_DevFamily= Virtex4 | PROP_DevDevice= xc4vsx25
PROP_DevFamilyPMName= virtex4 | PROP_ISimSimulationRunTime_behav_tb= 5000 ns
PROP_ISimSimulationRunTime_par_tb= 5000 ns | PROP_DevPackage= ff668
PROP_Synthesis_Tool= XST (VHDL/Verilog) | PROP_DevSpeed=-12
PROP_PreferredLanguage= Verilog | FILE_UCF= 1
FILE_USERDOC= 1 | FILE_VERILOG= 13

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG= 2 | NGDBUILD_NUM_DCM_ADV= 2 | NGDBUILD_NUM_FD= 1 | NGDBUILD_NUM_FDC= 146
NGDBUILD_NUM_FDCE= 72 | NGDBUILD_NUM_FDCP= 16 | NGDBUILD_NUM_FDP= 47 | NGDBUILD_NUM_FDPE= 8
NGDBUILD_NUM_FDR= 3 | NGDBUILD_NUM_GND= 1 | NGDBUILD_NUM_IBUF= 3 | NGDBUILD_NUM_IBUFG= 2
NGDBUILD_NUM_INV= 19 | NGDBUILD_NUM_IOBUF= 64 | NGDBUILD_NUM_LUT1= 1 | NGDBUILD_NUM_LUT2= 41
NGDBUILD_NUM_LUT2_D= 1 | NGDBUILD_NUM_LUT2_L= 2 | NGDBUILD_NUM_LUT3= 32 | NGDBUILD_NUM_LUT3_D= 2
NGDBUILD_NUM_LUT4= 35 | NGDBUILD_NUM_LUT4_D= 1 | NGDBUILD_NUM_LUT4_L= 4 | NGDBUILD_NUM_MUXCY= 15
NGDBUILD_NUM_MUXF5= 8 | NGDBUILD_NUM_OBUF= 23 | NGDBUILD_NUM_SRL16= 34 | NGDBUILD_NUM_VCC= 1
NGDBUILD_NUM_XORCY= 16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG= 2 | NGDBUILD_NUM_DCM_ADV= 2 | NGDBUILD_NUM_FD= 1 | NGDBUILD_NUM_FDC= 146
NGDBUILD_NUM_FDCE= 72 | NGDBUILD_NUM_FDCP= 16 | NGDBUILD_NUM_FDP= 47 | NGDBUILD_NUM_FDPE= 8
NGDBUILD_NUM_FDR= 3 | NGDBUILD_NUM_GND= 1 | NGDBUILD_NUM_IBUF= 67 | NGDBUILD_NUM_IBUFG= 2
NGDBUILD_NUM_INV= 19 | NGDBUILD_NUM_LUT1= 1 | NGDBUILD_NUM_LUT2= 41 | NGDBUILD_NUM_LUT2_D= 1
NGDBUILD_NUM_LUT2_L= 2 | NGDBUILD_NUM_LUT3= 32 | NGDBUILD_NUM_LUT3_D= 2 | NGDBUILD_NUM_LUT4= 35
NGDBUILD_NUM_LUT4_D= 1 | NGDBUILD_NUM_LUT4_L= 4 | NGDBUILD_NUM_MUXCY= 15 | NGDBUILD_NUM_MUXF5= 8
NGDBUILD_NUM_OBUF= 23 | NGDBUILD_NUM_OBUFT= 64 | NGDBUILD_NUM_SRLC16E= 34 | NGDBUILD_NUM_TS_TIMESPEC= 1
NGDBUILD_NUM_VCC= 1 | NGDBUILD_NUM_XORCY= 16

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj | -ifmt= mixed | -ofn=<design_top> | -ofmt= NGC
-p= xc4vsx25-12-ff668 | -top=<design_top> | -opt_mode= Speed | -opt_level= 1
-power= NO | -iuc= NO | -keep_hierarchy= No | -netlist_hierarchy= As_Optimized
-rtlview= Yes | -glob_opt= AllClockNets | -read_cores= YES | -write_timing_constraints= NO
-cross_clock_analysis= NO | -bus_delimiter=<> | -slice_utilization_ratio= 100 | -bram_utilization_ratio= 100
-dsp_utilization_ratio= 100 | -verilog2001= YES | -fsm_extract= YES | -fsm_encoding= Auto
-safe_implementation= No | -fsm_style= LUT | -ram_extract= Yes | -ram_style= Auto
-rom_extract= Yes | -shreg_extract= YES | -rom_style= Auto | -auto_bram_packing= NO
-resource_sharing= YES | -async_to_sync= NO | -use_dsp48= Auto | -iobuf= YES
-max_fanout= 100000 | -bufg= 32 | -register_duplication= YES | -register_balancing= No
-optimize_primitives= NO | -use_clock_enable= Auto | -use_sync_set= Auto | -use_sync_reset= Auto
-iob= Auto | -equivalent_register_removal= YES | -slice_utilization_ratio_maxmargin= 5