Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Thu Jun 19 19:15:49 2014

drc -z top.ncd top.pcf

WARNING:PhysDesignRules:372 - Gated clock. Clock net led_ct/clk_hz is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ADCLK_OBUF is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 2 warnings.  Please see the previously displayed
individual error or warning messages for more details.
