Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\led.v" into library work
Parsing module <led_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\beep.v" into library work
Parsing module <beep_module>.
Analyzing Verilog file "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\top.v" into library work
Parsing module <top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <top>.

Elaborating module <led_module>.

Elaborating module <beep_module>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\top.v".
        NUM_0 = 7'b0111111
        NUM_1 = 7'b0000110
        NUM_2 = 7'b1011011
        NUM_3 = 7'b1001111
        NUM_4 = 7'b1100110
        NUM_5 = 7'b1101101
        NUM_6 = 7'b1111101
        NUM_7 = 7'b0000111
        NUM_8 = 7'b1111111
        NUM_9 = 7'b1101111
        NUM_B = 7'b0000000
        EN_1 = 8'b00001110
        EN_2 = 8'b00001101
        EN_3 = 8'b00001011
        EN_4 = 8'b00000111
        EN_A = 4'b0000
    Summary:
	no macro.
Unit <top> synthesized.

Synthesizing Unit <led_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\led.v".
        SEC_TIME = 32'b00000010110111000110110000000000
    Found 1-bit register for signal <clk_hz>.
    Found 4-bit register for signal <led_reg>.
    Found 32-bit register for signal <cnt1>.
    Found 32-bit adder for signal <cnt1[31]_GND_2_o_add_2_OUT> created at line 35.
    Found 16x4-bit Read Only RAM for signal <PWR_2_o_PWR_2_o_mux_16_OUT>
    Found 1-bit tristate buffer for signal <led<3>> created at line 56
    Found 1-bit tristate buffer for signal <led<2>> created at line 56
    Found 1-bit tristate buffer for signal <led<1>> created at line 56
    Found 1-bit tristate buffer for signal <led<0>> created at line 56
    HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <led_reg> would allow inference of a finite state machine and as consequence better performance and smaller area.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  37 D-type flip-flop(s).
	inferred   4 Tristate(s).
Unit <led_module> synthesized.

Synthesizing Unit <beep_module>.
    Related source file is "E:\WorkSpace\Project\Demo_Board\Espier_III_Xilinx\document\00-Upload\6-Example\3-example_dt_1\beep.v".
        DIV_KHZ = 32'b00000000000000001011101110000000
    Found 1-bit register for signal <clk_1k>.
    Found 32-bit register for signal <cnt_khz>.
    Found 32-bit adder for signal <cnt_khz[31]_GND_7_o_add_2_OUT> created at line 26.
    Found 1-bit tristate buffer for signal <beep> created at line 28
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <beep_module> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 16x4-bit single-port Read Only RAM                    : 1
# Adders/Subtractors                                   : 2
 32-bit adder                                          : 2
# Registers                                            : 5
 1-bit register                                        : 2
 32-bit register                                       : 2
 4-bit register                                        : 1
# Tristates                                            : 5
 1-bit tristate buffer                                 : 5

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <beep_module>.
The following registers are absorbed into counter <cnt_khz>: 1 register on signal <cnt_khz>.
Unit <beep_module> synthesized (advanced).

Synthesizing (advanced) Unit <led_module>.
The following registers are absorbed into counter <cnt1>: 1 register on signal <cnt1>.
INFO:Xst:3231 - The small RAM <Mram_PWR_2_o_PWR_2_o_mux_16_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 4-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <led_reg>       |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <led_module> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 16x4-bit single-port distributed Read Only RAM        : 1
# Counters                                             : 2
 32-bit up counter                                     : 2
# Registers                                            : 6
 Flip-Flops                                            : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 70
 Flip-Flops                                            : 70

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 279
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 62
#      LUT2                        : 65
#      LUT3                        : 1
#      LUT4                        : 6
#      LUT5                        : 1
#      LUT6                        : 14
#      MUXCY                       : 62
#      VCC                         : 1
#      XORCY                       : 64
# FlipFlops/Latches                : 70
#      FD                          : 70
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      OBUF                        : 15
#      OBUFT                       : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:              70  out of  11440     0%  
 Number of Slice LUTs:                  151  out of   5720     2%  
    Number used as Logic:               151  out of   5720     2%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    151
   Number with an unused Flip Flop:      81  out of    151    53%  
   Number with an unused LUT:             0  out of    151     0%  
   Number of fully used LUT-FF pairs:    70  out of    151    46%  
   Number of unique control sets:         2

IO Utilization: 
 Number of IOs:                          18
 Number of bonded IOBs:                  17  out of    102    16%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
led_ct/clk_hz                      | NONE(led_ct/led_reg_3) | 4     |
CLK                                | BUFGP                  | 66    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 4.130ns (Maximum Frequency: 242.113MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 3.732ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'led_ct/clk_hz'
  Clock period: 1.714ns (frequency: 583.431MHz)
  Total number of paths / destination ports: 16 / 4
-------------------------------------------------------------------------
Delay:               1.714ns (Levels of Logic = 1)
  Source:            led_ct/led_reg_2 (FF)
  Destination:       led_ct/led_reg_3 (FF)
  Source Clock:      led_ct/clk_hz rising
  Destination Clock: led_ct/clk_hz rising

  Data Path: led_ct/led_reg_2 to led_ct/led_reg_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.962  led_ct/led_reg_2 (led_ct/led_reg_2)
     LUT4:I0->O            1   0.203   0.000  led_ct/Mram_PWR_2_o_PWR_2_o_mux_16_OUT31 (led_ct/Mram_PWR_2_o_PWR_2_o_mux_16_OUT3)
     FD:D                      0.102          led_ct/led_reg_3
    ----------------------------------------
    Total                      1.714ns (0.752ns logic, 0.962ns route)
                                       (43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 4.130ns (frequency: 242.113MHz)
  Total number of paths / destination ports: 3170 / 66
-------------------------------------------------------------------------
Delay:               4.130ns (Levels of Logic = 3)
  Source:            led_ct/cnt1_25 (FF)
  Destination:       led_ct/clk_hz (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: led_ct/cnt1_25 to led_ct/clk_hz
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.447   0.981  led_ct/cnt1_25 (led_ct/cnt1_25)
     LUT6:I0->O            2   0.203   0.961  led_ct/cnt1[31]_GND_2_o_equal_2_o<31>5 (led_ct/cnt1[31]_GND_2_o_equal_2_o<31>4)
     LUT6:I1->O           17   0.203   1.028  led_ct/cnt1[31]_GND_2_o_equal_2_o<31>7 (led_ct/cnt1[31]_GND_2_o_equal_2_o)
     LUT2:I1->O            1   0.205   0.000  led_ct/cnt1_0_rstpot (led_ct/cnt1_0_rstpot)
     FD:D                      0.102          led_ct/cnt1_0
    ----------------------------------------
    Total                      4.130ns (1.160ns logic, 2.970ns route)
                                       (28.1% logic, 71.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.634ns (Levels of Logic = 1)
  Source:            beep_ct/clk_1k (FF)
  Destination:       BP1 (PAD)
  Source Clock:      CLK rising

  Data Path: beep_ct/clk_1k to BP1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.447   0.616  beep_ct/clk_1k (beep_ct/clk_1k)
     OBUFT:I->O                2.571          BP1_OBUFT (BP1)
    ----------------------------------------
    Total                      3.634ns (3.018ns logic, 0.616ns route)
                                       (83.0% logic, 17.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'led_ct/clk_hz'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              3.732ns (Levels of Logic = 1)
  Source:            led_ct/led_reg_0 (FF)
  Destination:       LED1 (PAD)
  Source Clock:      led_ct/clk_hz rising

  Data Path: led_ct/led_reg_0 to LED1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               5   0.447   0.714  led_ct/led_reg_0 (led_ct/led_reg_0)
     OBUF:I->O                 2.571          LED1_OBUF (LED1)
    ----------------------------------------
    Total                      3.732ns (3.018ns logic, 0.714ns route)
                                       (80.9% logic, 19.1% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    4.130|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock led_ct/clk_hz
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
led_ct/clk_hz  |    1.714|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.66 secs
 
--> 

Total memory usage is 257936 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)

