Xilinx Design Summary

top Project Status
Project File: | top.xise | Parser Errors: | No Errors
Module Name: | top | Implementation State: | Programming File Generated

Target Device:

xc6slx9-3tqg144

- Errors:

No Errors

Product Version:

ISE 14.7

- Warnings:

No Warnings

Design Goal:

Balanced

- Routing Results:

All Signals Completely Routed

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

Environment:

System Settings

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 0 | 11,440 | 0% |
Number of Slice LUTs | 0 | 5,720 | 0% |
Number of occupied Slices | 0 | 1,430 | 0% |
Number of MUXCYs used | 0 | 2,860 | 0% |
Number of LUT Flip Flop pairs used | 0 |  |  |
Number of bonded IOBs | 4 | 102 | 3% |
Number of LOCed IOBs | 4 | 4 | 100% |
Number of RAMB16BWERs | 0 | 32 | 0% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 0 | 16 | 0% |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: |  |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周五 六月 20 21:45:22 2014 | 0 | 0 | 0
Translation Report | Current | 周五 六月 20 21:45:29 2014 | 0 | 0 | 0
Map Report | Current | 周五 六月 20 21:45:39 2014 | 0 | 0 | 6 Infos (0 new)
Place and Route Report | Current | 周五 六月 20 21:45:48 2014 | 0 | 0 | 2 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | 周五 六月 20 21:45:55 2014 | 0 | 0 | 4 Infos (0 new)
Bitgen Report | Current | 周五 六月 20 21:46:05 2014 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | 周五 六月 20 21:46:06 2014
WebTalk Log File | Current | 周五 六月 20 21:46:17 2014

Date Generated: 06/20/2014 -