#-----------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
# Start of session at: Wed Apr 16 23:02:31 2014
# Process ID: 4384
# Log file: E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/planAhead_run_1/planAhead.log
# Journal file: E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from D:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [D:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [D:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/pa.fromNetlist.tcl
# create_project -name top -dir "E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/planAhead_run_1" -part xc6slx9tqg144-3
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
# set_property edif_top_file "E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/top.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x} {ipcore_dir} }
# set_property target_constrs_file "top.ucf" [current_fileset -constrset]
Adding file 'E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/top.ucf' to fileset 'constrs_1'
# add_files [list {top.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc6slx9tqg144-3
Release 14.7 - ngc2edif P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Reading design top.ngc ...
WARNING:NetListWriters:298 - No output is written to top.xncf, ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus ir_ct/IR_Value<15 : 0> on block top is
   not reconstructed, because there are some missing bus signals.
  finished :Prep
Writing EDIF netlist file top.edif ...
ngc2edif: Total memory usage is 83648 kilobytes

Parsing EDIF File [./planAhead_run_1/top.data/cache/top_ngc_zx.edif]
Finished Parsing EDIF File [./planAhead_run_1/top.data/cache/top_ngc_zx.edif]
WARNING: [Netlist 29-43] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' defined in file 'top.ngc' contains large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.
Loading clock regions from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
Loading clock buffers from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
Loading package pin functions from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/PinFunctions.xml...
Loading package from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
Loading io standards from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from D:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : D:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan6/drc.xml
Parsing UCF File [E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/top.ucf]
Finished Parsing UCF File [E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x/top.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 342c3342
link_design: Time (s): elapsed = 00:00:19 . Memory (MB): peak = 657.941 ; gain = 181.078
exit
ERROR: [PlanAhead 12-106] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
 (See E:/WorkSpace/Project/Demo_Board/Espier_III_Xilinx/logic/0-example_test_board_x\planAhead_pid4384.debug)
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Wed Apr 16 23:04:35 2014...
INFO: [Common 17-83] Releasing license: PlanAhead
