Xilinx Design Summary

wave_gen Project Status
Project File: | wave_gen_ver_s6.xise | Parser Errors: | No Errors
Module Name: | wave_gen | Implementation State: | New

Target Device:

xc6slx45t-2fgg484

- Errors:

Product Version:

ISE 14.7

- Warnings:

Design Goal:

Balanced

- Routing Results:

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

Environment:

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 06/09/2014 - 22:12:23