Xilinx Design Summary

freqm Project Status
Project File: | freqm.xise | Parser Errors: | No Errors
Module Name: | freqm | Implementation State: | New

Target Device:

xc3s100e-4vq100

- Errors:

Product Version:

ISE 14.7

- Warnings:

Design Goal:

Balanced

- Routing Results:

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

Environment:

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/25/2014 - 23:48:25