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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
// Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1    40.001      0.000      50.0      289.232    235.401
// CLK_OUT2    16.000      0.000      50.0      348.901    235.401
// CLK_OUT3     5.107      0.000      50.0      436.954    235.401
//
//----------------------------------------------------------------------------
// Input Clock   Input Freq (MHz)   Input Jitter (UI)
//----------------------------------------------------------------------------
// primary              48            0.010

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  clk_pll instance_name
   (// Clock in ports
    .CLK_IN1            (CLK_IN1),      // IN
    // Clock out ports
    .CLK_OUT1           (CLK_OUT1),     // OUT
    .CLK_OUT2           (CLK_OUT2),     // OUT
    .CLK_OUT3           (CLK_OUT3),     // OUT
    // Status and control signals
    .RESET              (RESET),        // IN
    .LOCKED             (LOCKED));      // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
