Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.35 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.35 secs
 
--> Reading design: sdrm.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "sdrm.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "sdrm"
Output Format                      : NGC
Target Device                      : xc4vsx25-12-ff668

---- Source Options
Top Module Name                    : sdrm
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : 16
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "define.v" in library work
Compiling verilog file "sdrmc_state.v" in library work
Compiling verilog file "ref_cntr.v" in library work
Module <sdrmc_state> compiled
Compiling verilog file "rcd_cntr.v" in library work
Module <ref_cntr> compiled
Compiling verilog file "ki_cntr.v" in library work
Module <rcd_cntr> compiled
Compiling verilog file "cslt_cntr.v" in library work
Module <ki_cntr> compiled
Compiling verilog file "brst_cntr.v" in library work
Module <cslt_cntr> compiled
Compiling verilog file "sys_int.v" in library work
Compiling verilog include file "define.v"
Module <brst_cntr> compiled
Compiling verilog file "sdrm_t.v" in library work
Module <sys_int> compiled
Compiling verilog file "sdrm.v" in library work
Compiling verilog include file "define.v"
Module <sdrm_t> compiled
Module <sdrm> compiled
No errors in compilation
Analysis of file <"sdrm.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <sdrm> in library <work>.

Analyzing hierarchy for module <sdrm_t> in library <work>.

Analyzing hierarchy for module <sys_int> in library <work>.

Analyzing hierarchy for module <sdrmc_state> in library <work>.

Analyzing hierarchy for module <cslt_cntr> in library <work>.

Analyzing hierarchy for module <brst_cntr> in library <work>.

Analyzing hierarchy for module <rcd_cntr> in library <work>.

Analyzing hierarchy for module <ref_cntr> in library <work>.

Analyzing hierarchy for module <ki_cntr> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <sdrm>.
WARNING:Xst:916 - "sdrm.v" line 162: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm.v" line 165: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm.v" line 166: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm.v" line 167: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm.v" line 168: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <sdrm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ibufg0> in unit <sdrm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <ibufg0> in unit <sdrm>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <ibufg0> in unit <sdrm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <ibufg0> in unit <sdrm>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ibufg1> in unit <sdrm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <ibufg1> in unit <sdrm>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <ibufg1> in unit <sdrm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <ibufg1> in unit <sdrm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKIN_PERIOD =  10.000000" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dll0> in unit <sdrm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <dll0> in unit <sdrm>.
    Set user-defined property "FACTORY_JF =  F0F0" for instance <dll0> in unit <sdrm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dll0> in unit <sdrm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <dll0> in unit <sdrm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLKIN_PERIOD =  10.000000" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dll1> in unit <sdrm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <dll1> in unit <sdrm>.
    Set user-defined property "FACTORY_JF =  F0F0" for instance <dll1> in unit <sdrm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dll1> in unit <sdrm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <dll1> in unit <sdrm>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <rst_b> in unit <sdrm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <rst_b> in unit <sdrm>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <rst_b> in unit <sdrm>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <rst_b> in unit <sdrm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <rst_b> in unit <sdrm>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ads_b> in unit <sdrm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <ads_b> in unit <sdrm>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <ads_b> in unit <sdrm>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <ads_b> in unit <sdrm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <ads_b> in unit <sdrm>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <wern_b> in unit <sdrm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <wern_b> in unit <sdrm>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <wern_b> in unit <sdrm>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <wern_b> in unit <sdrm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <wern_b> in unit <sdrm>.
Analyzing module <sdrm_t> in library <work>.
WARNING:Xst:916 - "sdrm_t.v" line 136: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm_t.v" line 137: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm_t.v" line 138: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm_t.v" line 139: Delay is ignored for synthesis.
WARNING:Xst:916 - "sdrm_t.v" line 142: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <sdrm_t> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <SRL16> in unit <sdrm_t>.
    Set user-defined property "INIT =  0000" for instance <I_AD_tri> in unit <sdrm_t>.
Analyzing module <sdrmc_state> in library <work>.
"sdrmc_state.v" line 107: Found FullParallel Case directive in module <sdrmc_state>.
"sdrmc_state.v" line 105: Found FullParallel Case directive in module <sdrmc_state>.
Module <sdrmc_state> is correct for synthesis.
 
Analyzing module <cslt_cntr> in library <work>.
Module <cslt_cntr> is correct for synthesis.
 
Analyzing module <brst_cntr> in library <work>.
Module <brst_cntr> is correct for synthesis.
 
Analyzing module <rcd_cntr> in library <work>.
Module <rcd_cntr> is correct for synthesis.
 
Analyzing module <ref_cntr> in library <work>.
Module <ref_cntr> is correct for synthesis.
 
Analyzing module <ki_cntr> in library <work>.
Module <ki_cntr> is correct for synthesis.
 
Analyzing module <sys_int> in library <work>.
Module <sys_int> is correct for synthesis.
 
    Set user-defined property "INIT =  0000" for instance <SRL16_0> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_1> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_2> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_3> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_4> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_5> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_6> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_7> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_8> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_9> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_10> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_11> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_12> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_13> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_14> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_15> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_16> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_17> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_18> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_19> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_20> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_21> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_22> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_23> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_24> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_25> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_26> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_27> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_28> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_29> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_30> in unit <sys_int>.
    Set user-defined property "INIT =  0000" for instance <SRL16_31> in unit <sys_int>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <sdrmc_state>.
    Related source file is "sdrmc_state.v".
    Found 13-bit register for signal <state>.
Unit <sdrmc_state> synthesized.


Synthesizing Unit <cslt_cntr>.
    Related source file is "cslt_cntr.v".
    Found 2-bit register for signal <count>.
    Found 2-bit subtractor for signal <count_N$addsub0000> created at line 53.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cslt_cntr> synthesized.


Synthesizing Unit <brst_cntr>.
    Related source file is "brst_cntr.v".
    Found 3-bit register for signal <count>.
    Found 3-bit subtractor for signal <count_N$addsub0000> created at line 55.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <brst_cntr> synthesized.


Synthesizing Unit <rcd_cntr>.
    Related source file is "rcd_cntr.v".
    Found 2-bit register for signal <count>.
    Found 2-bit subtractor for signal <count_N$addsub0000> created at line 54.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <rcd_cntr> synthesized.


Synthesizing Unit <ref_cntr>.
    Related source file is "ref_cntr.v".
    Found 1-bit register for signal <auto_ref>.
    Found 1-bit register for signal <p_auto_ref>.
    Found 16-bit subtractor for signal <count_N$addsub0000> created at line 59.
    Found 16-bit register for signal <rcount>.
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ref_cntr> synthesized.


Synthesizing Unit <ki_cntr>.
    Related source file is "ki_cntr.v".
    Found 4-bit register for signal <count>.
    Found 4-bit subtractor for signal <count_N$addsub0000> created at line 54.
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ki_cntr> synthesized.


Synthesizing Unit <sdrm_t>.
    Related source file is "sdrm_t.v".
    Found 1-bit register for signal <Locked_i>.
    Found 1-bit register for signal <sd_ba_o>.
    Found 4-bit register for signal <sd_doe_n>.
    Found 1-bit register for signal <sd_we_o>.
    Found 11-bit register for signal <sd_add_o>.
    Found 1-bit register for signal <sd_ras_o>.
    Found 1-bit register for signal <ready_o>.
    Found 1-bit register for signal <sd_cas_o>.
    Found 1-bit register for signal <clr_ref_d>.
    Found 1-bit register for signal <ld_brst>.
    Found 1-bit register for signal <ld_cslt>.
    Found 1-bit register for signal <ld_rcd>.
    Found 1-bit register for signal <sd_add_mx>.
    Summary:
	inferred  26 D-type flip-flop(s).
Unit <sdrm_t> synthesized.


Synthesizing Unit <sys_int>.
    Related source file is "sys_int.v".
WARNING:Xst:647 - Input <we_rn_reg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <data_addr_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <cntrl<31:28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cntrl<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 4x3-bit ROM for signal <Act_st$mux0000> created at line 72.
    Found 3-bit register for signal <Act_st>.
    Found 32-bit register for signal <Add_reg>.
    Found 32-bit register for signal <cntrl>.
    Found 32-bit register for signal <Data_reg>.
    Found 1-bit register for signal <ld_cnt_reg>.
    Summary:
	inferred   1 ROM(s).
	inferred  68 D-type flip-flop(s).
Unit <sys_int> synthesized.


Synthesizing Unit <sdrm>.
    Related source file is "sdrm.v".
WARNING:Xst:646 - Signal <unused3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <unused2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <unused1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ready_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rcd_end> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <kid> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Locked_j> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Add_reg<31:22>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Add_reg<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Register <sd_data_t<1>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<2>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<3>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<4>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<5>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<6>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<7>> equivalent to <sd_data_t<0>> has been removed
    Register <sd_data_t<11>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<12>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<13>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<14>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<15>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<8>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<9>> equivalent to <sd_data_t<10>> has been removed
    Register <sd_data_t<17>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<18>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<19>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<20>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<21>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<22>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<23>> equivalent to <sd_data_t<16>> has been removed
    Register <sd_data_t<25>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<26>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<27>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<28>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<29>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<30>> equivalent to <sd_data_t<24>> has been removed
    Register <sd_data_t<31>> equivalent to <sd_data_t<24>> has been removed
    Found 32-bit register for signal <AD_o>.
    Found 32-bit register for signal <AD_reg>.
    Found 1-bit register for signal <data_addr_n_reg>.
    Found 11-bit register for signal <sd_add_o>.
    Found 1-bit register for signal <sd_ba_o>.
    Found 1-bit register for signal <sd_cas_o>.
    Found 32-bit register for signal <sd_data_o>.
    Found 32-bit register for signal <sd_data_R>.
    Found 1-bit register for signal <sd_data_t<24>>.
    Found 1-bit register for signal <sd_data_t<16>>.
    Found 1-bit register for signal <sd_data_t<10>>.
    Found 1-bit register for signal <sd_data_t<0>>.
    Found 4-bit register for signal <sd_doe_n>.
    Found 1-bit register for signal <sd_ras_o>.
    Found 1-bit register for signal <sd_we_o>.
    Found 1-bit register for signal <we_rn_reg>.
    Summary:
	inferred 153 D-type flip-flop(s).
Unit <sdrm> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x3-bit ROM                                           : 1
# Adders/Subtractors                                   : 5
 16-bit subtractor                                     : 1
 2-bit subtractor                                      : 2
 3-bit subtractor                                      : 1
 4-bit subtractor                                      : 1
# Registers                                            : 57
 1-bit register                                        : 40
 11-bit register                                       : 2
 13-bit register                                       : 1
 2-bit register                                        : 2
 3-bit register                                        : 2
 32-bit register                                       : 7
 4-bit register                                        : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:2261 - The FF/Latch <sd_doe_n_0> in Unit <sdrm_t> is equivalent to the following 3 FFs/Latches, which will be removed : <sd_doe_n_1> <sd_doe_n_2> <sd_doe_n_3> 
WARNING:Xst:2677 - Node <Add_reg_0> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_1> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_22> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_23> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_24> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_25> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_26> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_27> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_28> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_29> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_30> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <Add_reg_31> of sequential type is unconnected in block <sys_int>.

Synthesizing (advanced) Unit <sys_int>.
INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_Act_st_mux0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
Unit <sys_int> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x3-bit ROM                                           : 1
# Adders/Subtractors                                   : 5
 16-bit subtractor                                     : 1
 2-bit subtractor                                      : 2
 3-bit subtractor                                      : 1
 4-bit subtractor                                      : 1
# Registers                                            : 321
 Flip-Flops                                            : 321

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <sd_doe_n_0> in Unit <sdrm_t> is equivalent to the following 3 FFs/Latches, which will be removed : <sd_doe_n_1> <sd_doe_n_2> <sd_doe_n_3> 
INFO:Xst:1901 - Instance dll0 in unit sdrm of type DCM_BASE has been replaced by DCM_ADV
INFO:Xst:1901 - Instance dll1 in unit sdrm of type DCM_BASE has been replaced by DCM_ADV
WARNING:Xst:2677 - Node <cntrl_31> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <cntrl_30> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <cntrl_29> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <cntrl_28> of sequential type is unconnected in block <sys_int>.
WARNING:Xst:2677 - Node <cntrl_7> of sequential type is unconnected in block <sys_int>.

Optimizing unit <sdrm> ...

Optimizing unit <brst_cntr> ...

Optimizing unit <ref_cntr> ...

Optimizing unit <ki_cntr> ...

Optimizing unit <sdrmc_state> ...

Optimizing unit <sys_int> ...

Optimizing unit <sdrm_t> ...
WARNING:Xst:2677 - Node <we_rn_reg> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_31> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_30> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_29> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_28> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_27> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_26> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_25> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_24> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_23> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_22> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_1> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sys_int/Add_reg_0> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sdrm_t/ref_cntr/p_auto_ref> of sequential type is unconnected in block <sdrm>.
WARNING:Xst:2677 - Node <sdrm_t/ready_o> of sequential type is unconnected in block <sdrm>.

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <sd_doe_n_0> in Unit <sdrm> is equivalent to the following 3 FFs/Latches, which will be removed : <sd_doe_n_1> <sd_doe_n_2> <sd_doe_n_3> 
INFO:Xst:2261 - The FF/Latch <sd_data_t_24> in Unit <sdrm> is equivalent to the following 3 FFs/Latches, which will be removed : <sd_data_t_16> <sd_data_t_10> <sd_data_t_0> 
Found area constraint ratio of 100 (+ 5) on block sdrm, actual ratio is 1.
FlipFlop data_addr_n_reg has been replicated 1 time(s)
INFO:Xst:1843 - HDL ADVISOR - FlipFlop data_addr_n_reg connected to a primary input has been replicated

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 293
 Flip-Flops                                            : 293

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sdrm.ngr
Top Level Output File Name         : sdrm
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 92

Cell Usage :
# BELS                             : 179
#      GND                         : 1
#      INV                         : 19
#      LUT1                        : 1
#      LUT2                        : 41
#      LUT2_D                      : 1
#      LUT2_L                      : 2
#      LUT3                        : 32
#      LUT3_D                      : 2
#      LUT4                        : 35
#      LUT4_D                      : 1
#      LUT4_L                      : 4
#      MUXCY                       : 15
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 293
#      FD                          : 1
#      FDC                         : 146
#      FDCE                        : 72
#      FDCP                        : 16
#      FDP                         : 47
#      FDPE                        : 8
#      FDR                         : 3
# Shift Registers                  : 34
#      SRL16                       : 34
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 92
#      IBUF                        : 3
#      IBUFG                       : 2
#      IOBUF_F_12                  : 64
#      OBUF_F_12                   : 22
#      OBUF_F_16                   : 1
# DCM_ADVs                         : 2
#      DCM_ADV                     : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx25ff668-12 

 Number of Slices:                      185  out of  10240     1%  
 Number of Slice Flip Flops:            293  out of  20480     1%  
 Number of 4 input LUTs:                172  out of  20480     0%  
    Number used as logic:               138
    Number used as Shift registers:      34
 Number of IOs:                          92
 Number of bonded IOBs:                  92  out of    320    28%  
 Number of GCLKs:                         2  out of     32     6%  
 Number of DCM_ADVs:                      2  out of      4    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clkp                               | dll1:CLK2X             | 309   |
Clkp                               | dll1:CLK0              | 18    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------+--------------------------------+-------+
Control Signal                                                         | Buffer(FF name)                | Load  |
-----------------------------------------------------------------------+--------------------------------+-------+
Locked_i_inv(sys_int/Locked_inv1_INV_0:O)                              | NONE(AD_o_0)                   | 272   |
sdrm_t/ref_cntr/Reset_inv(sdrm_t/ref_cntr/Reset_inv1_INV_0:O)          | NONE(sdrm_t/ref_cntr/auto_ref) | 1     |
sdrm_t/ref_cntr/rcount_0_and0000(sdrm_t/ref_cntr/rcount_0_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_0) | 1     |
sdrm_t/ref_cntr/rcount_0_and0001(sdrm_t/ref_cntr/rcount_0_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_0) | 1     |
sdrm_t/ref_cntr/rcount_10_and0000(sdrm_t/ref_cntr/rcount_10_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_10)| 1     |
sdrm_t/ref_cntr/rcount_10_and0001(sdrm_t/ref_cntr/rcount_10_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_10)| 1     |
sdrm_t/ref_cntr/rcount_11_and0000(sdrm_t/ref_cntr/rcount_11_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_11)| 1     |
sdrm_t/ref_cntr/rcount_11_and0001(sdrm_t/ref_cntr/rcount_11_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_11)| 1     |
sdrm_t/ref_cntr/rcount_12_and0000(sdrm_t/ref_cntr/rcount_12_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_12)| 1     |
sdrm_t/ref_cntr/rcount_12_and0001(sdrm_t/ref_cntr/rcount_12_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_12)| 1     |
sdrm_t/ref_cntr/rcount_13_and0000(sdrm_t/ref_cntr/rcount_13_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_13)| 1     |
sdrm_t/ref_cntr/rcount_13_and0001(sdrm_t/ref_cntr/rcount_13_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_13)| 1     |
sdrm_t/ref_cntr/rcount_14_and0000(sdrm_t/ref_cntr/rcount_14_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_14)| 1     |
sdrm_t/ref_cntr/rcount_14_and0001(sdrm_t/ref_cntr/rcount_14_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_14)| 1     |
sdrm_t/ref_cntr/rcount_15_and0000(sdrm_t/ref_cntr/rcount_15_and00001:O)| NONE(sdrm_t/ref_cntr/rcount_15)| 1     |
sdrm_t/ref_cntr/rcount_15_and0001(sdrm_t/ref_cntr/rcount_15_and00011:O)| NONE(sdrm_t/ref_cntr/rcount_15)| 1     |
sdrm_t/ref_cntr/rcount_1_and0000(sdrm_t/ref_cntr/rcount_1_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_1) | 1     |
sdrm_t/ref_cntr/rcount_1_and0001(sdrm_t/ref_cntr/rcount_1_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_1) | 1     |
sdrm_t/ref_cntr/rcount_2_and0000(sdrm_t/ref_cntr/rcount_2_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_2) | 1     |
sdrm_t/ref_cntr/rcount_2_and0001(sdrm_t/ref_cntr/rcount_2_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_2) | 1     |
sdrm_t/ref_cntr/rcount_3_and0000(sdrm_t/ref_cntr/rcount_3_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_3) | 1     |
sdrm_t/ref_cntr/rcount_3_and0001(sdrm_t/ref_cntr/rcount_3_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_3) | 1     |
sdrm_t/ref_cntr/rcount_4_and0000(sdrm_t/ref_cntr/rcount_4_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_4) | 1     |
sdrm_t/ref_cntr/rcount_4_and0001(sdrm_t/ref_cntr/rcount_4_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_4) | 1     |
sdrm_t/ref_cntr/rcount_5_and0000(sdrm_t/ref_cntr/rcount_5_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_5) | 1     |
sdrm_t/ref_cntr/rcount_5_and0001(sdrm_t/ref_cntr/rcount_5_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_5) | 1     |
sdrm_t/ref_cntr/rcount_6_and0000(sdrm_t/ref_cntr/rcount_6_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_6) | 1     |
sdrm_t/ref_cntr/rcount_6_and0001(sdrm_t/ref_cntr/rcount_6_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_6) | 1     |
sdrm_t/ref_cntr/rcount_7_and0000(sdrm_t/ref_cntr/rcount_7_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_7) | 1     |
sdrm_t/ref_cntr/rcount_7_and0001(sdrm_t/ref_cntr/rcount_7_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_7) | 1     |
sdrm_t/ref_cntr/rcount_8_and0000(sdrm_t/ref_cntr/rcount_8_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_8) | 1     |
sdrm_t/ref_cntr/rcount_8_and0001(sdrm_t/ref_cntr/rcount_8_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_8) | 1     |
sdrm_t/ref_cntr/rcount_9_and0000(sdrm_t/ref_cntr/rcount_9_and00001:O)  | NONE(sdrm_t/ref_cntr/rcount_9) | 1     |
sdrm_t/ref_cntr/rcount_9_and0001(sdrm_t/ref_cntr/rcount_9_and00011:O)  | NONE(sdrm_t/ref_cntr/rcount_9) | 1     |
-----------------------------------------------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 4.202ns (Maximum Frequency: 237.988MHz)
   Minimum input arrival time before clock: 1.364ns
   Maximum output required time after clock: 4.573ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Clkp'
  Clock period: 4.202ns (frequency: 237.988MHz)
  Total number of paths / destination ports: 940 / 342
-------------------------------------------------------------------------
Delay:               2.101ns (Levels of Logic = 3)
  Source:            sdrm_t/ki_cntr/count_3 (FF)
  Destination:       sdrm_t/sdrm_st/state_2 (FF)
  Source Clock:      Clkp rising 2.0X
  Destination Clock: Clkp rising 2.0X

  Data Path: sdrm_t/ki_cntr/count_3 to sdrm_t/sdrm_st/state_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.272   0.571  sdrm_t/ki_cntr/count_3 (sdrm_t/ki_cntr/count_3)
     LUT4_D:I0->O          3   0.147   0.399  sdrm_t/ki_cntr/count_N_cmp_eq00001 (sdrm_t/ki_end)
     LUT3_D:I2->O          2   0.147   0.401  sdrm_t/sdrm_st/next_state_4_mux000011 (sdrm_t/sdrm_st/N01)
     LUT3:I2->O            1   0.147   0.000  sdrm_t/sdrm_st/next_state_3_mux00001 (sdrm_t/sdrm_st/next_state<3>)
     FDC:D                     0.017          sdrm_t/sdrm_st/state_2
    ----------------------------------------
    Total                      2.101ns (0.730ns logic, 1.371ns route)
                                       (34.7% logic, 65.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clkp'
  Total number of paths / destination ports: 70 / 70
-------------------------------------------------------------------------
Offset:              1.364ns (Levels of Logic = 2)
  Source:            we_rn (PAD)
  Destination:       sdrm_t/sdrm_st/state_11 (FF)
  Destination Clock: Clkp rising 2.0X

  Data Path: we_rn to sdrm_t/sdrm_st/state_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.754   0.446  wern_b (we_rn_i)
     LUT4:I2->O            1   0.147   0.000  sdrm_t/sdrm_st/next_state_8_mux00001 (sdrm_t/sdrm_st/next_state<8>)
     FDC:D                     0.017          sdrm_t/sdrm_st/state_7
    ----------------------------------------
    Total                      1.364ns (0.918ns logic, 0.446ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clkp'
  Total number of paths / destination ports: 143 / 79
-------------------------------------------------------------------------
Offset:              4.573ns (Levels of Logic = 1)
  Source:            sdrm_t/I_AD_tri (FF)
  Destination:       AD<31> (PAD)
  Source Clock:      Clkp rising 2.0X

  Data Path: sdrm_t/I_AD_tri to AD<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q         32   1.802   0.686  sdrm_t/I_AD_tri (AD_tri)
     IOBUF_F_12:T->IO          2.085          ad0 (AD<0>)
    ----------------------------------------
    Total                      4.573ns (3.887ns logic, 0.686ns route)
                                       (85.0% logic, 15.0% route)

=========================================================================


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.65 secs
 
--> 

Total memory usage is 301252 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   57 (   0 filtered)
Number of infos    :    8 (   0 filtered)

