Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

WIN-IK5F4P909FE::  Fri Jun 20 21:45:42 2014

par -w -intstyle ise -ol high -mt off top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment D:\Xilinx\14.7\ISE_DS\ISE\.
   "top" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          0 out of   5,720    0%

Slice Logic Distribution:
  Number of occupied Slices:                     0 out of   1,430    0%
  Number of MUXCYs used:                         0 out of   2,860    0%
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                         4 out of     102    3%
    Number of LOCed IOBs:                        4 out of       4  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router


Phase  1  : 4 unrouted;      REAL time: 4 secs 

Phase  2  : 4 unrouted;      REAL time: 4 secs 

Phase  3  : 0 unrouted;      REAL time: 5 secs 

Phase  4  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Updating file: top.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 
Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)



Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  381 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file top.ncd



PAR done!
